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Author SHA1 Message Date
ghidra1 517c3d8f0c GP-928 SPARC language changes. Resolved FPSR duplicate reg name and 
cleaned-up ASR read write instructions.
 2021-05-06 13:21:46 -04:00
ghidra1 3b867b3444 Merge remote-tracking branch 'origin/GP-653_caheckman_UserDefinedCspec' 2021-05-06 12:41:24 -04:00
Cameron Taylor 3a8b4bd639
HCS12: Fix IDX1 addressing with negative immediate 2021-05-05 20:19:04 -04:00
ghidra1 f7b2d49468 Corrected various language errors (PPC, SPARC, MCS96) 2021-05-04 23:24:56 -04:00
caheckman a5d4ca3cab Program specific, user-defined, cspec extensions 
Documentation for spec extensions

Handle extensions with parse errors
Export button for spec extensions
Pop-up dialog for parse errors in user-defined specification extensions
GP-653 corrected some minor issues and established new ProgramDB version
make incremental initialization constructor for AddressSized private
Make AddressSized fields private
More adjustments to AddressSized
Review fixes for BasicCompilerSpec
Take restoreXml out of DataOrganization interface
Remove restoreXml from BitFieldPacking interface
More review fixes
Prevent callotherfixup extension with non-existent target
Suggested export name
More documentation for SpecExtension
Support for undo/redo with spec extensions
Documentation for ConstructTpl
Split out ProgramCompilerSpec and other changes for review
Changes after next round of reviews
 2021-05-04 12:11:55 -04:00
ghidorahrex b7a6607464 Fixed issue with PPAGE register not being properly restored afer CALL 
instructions in HCS12
 2021-05-04 11:52:52 -04:00
ghidra1 a34644abdc Merge branch 'GP-901_ghidra1_RegisterAlias' (Closes #2956) 2021-04-30 19:42:04 -04:00
ghidra1 774f5c345a Merge branch 'GP-902_ghidra1_ElfAbsoluteSymbols' 2021-04-30 19:41:15 -04:00
ghidra1 0a85fb1984 GP-902 Modified treatment of ELF Symbols which refer to SHN_UNDEF (0) or 
SHN_ABS (0xfff1) section index values.
 2021-04-30 11:34:40 -04:00
ghidra1 a40370ab7a Revert "Merge remote-tracking branch 'origin/GP-653_UserDefinedCspec--SQUASHED'" 2021-04-30 10:34:54 -04:00
ghidra1 b7499e1bc1 Merge remote-tracking branch 'origin/GT-3668_ghidorahrex_ppc_vle_simm20' 2021-04-29 17:08:23 -04:00
caheckman ed82c2cb34 GP-653 added support for user-defined compiler spec extensions 2021-04-29 16:17:25 -04:00
ghidra1 8f9b067384 GP-901 added regiater alias support and defined WREG aliases for PIC24 
variants
 2021-04-28 16:04:03 -04:00
ghidra1 74a580191e GP-906 corrected alignment of PIC24 allocated external symbol during ELF 
import
 2021-04-28 16:01:34 -04:00
ghidorahrex 0b7a00e10b Addex 's' suffix for ARM thumb instructions which modify status flags. 2021-04-23 14:21:27 -04:00
ghidra1 a9a6ecd56c Merge remote-tracking branch 
'origin/GP-800_ghidorahrex_x86_64_address_mode_fix' (Closes #2504)
 2021-04-23 11:40:50 -04:00
ghidra1 2c5ecf12d0 Merge remote-tracking branch 'origin/GP-837_ghidorahrex_PR-1163_toshipiazza_x86-sleigh-jcc' 2021-04-23 11:23:31 -04:00
Cameron Taylor c8322ba9e7
V850: Fixed multiply by immediate 
Multiply by immediate (mul imm9, reg2, reg3) used a signed token for the lower 5 bits of the immediate value imm9.
This resulted in any immediate value in which the 5th bit was set to be calculated incorrectly.

imm9 = 0x18 ( 0b000011000 )
OLD:    f8 0f 40 52        mul    -0x8, r1, r10
NEW:   f8 0f 40 52        mul    0x18, r1, r10

imm9 = -0xF0 ( 0b100010000 )
OLD:    f0 0f 60 52        mul    -0x10, r1, r10
NEW:   f0 0f 60 52        mul    -0xf0, r1, r10
 2021-04-22 20:50:11 -04:00
ghidra1 a372f17736 Merge remote-tracking branch 
'origin/GP-841_ghidorahrex_pic16_missing_instructions' (Closes #1362)
 2021-04-21 19:11:58 -04:00
ghidra1 1e39c2ac82 Merge remote-tracking branch 'origin/patch' 2021-04-20 17:33:40 -04:00
ghidra1 baeef06672 Certification cleanup 2021-04-20 17:15:14 -04:00
VGKintsugi 0f50356e73
SuperH: Div1 Code Review Changes 2021-04-17 03:03:36 -04:00
ghidorahrex fc3fef823d Restored unpackSRL macro to return instructions. 2021-04-15 07:34:45 -04:00
ghidorahrex 84f0096e02 Fixed size for signed immediate value of the PPC VLE e_li instruction 2021-04-13 12:30:10 -04:00
ghidorahrex 18eb9bc2d2 Added missing PIC16 instructions 2021-04-12 10:52:52 -04:00
Robert Xiao d9a291ff0e
Update PowerISA.idx with correct "physical" pages 
PowerISA.idx was incorrectly using "logical" page numbers for the listings, which would not come up correctly when called from the "Processor Manuals" menu. Fixed to apply "physical" page numbering, and tested with instructions from compiling [power8.s](https://chromium.googlesource.com/chromiumos/third_party/binutils/+/refs/heads/master/gas/testsuite/gas/ppc/power8.s) and [vle.s](https://chromium.googlesource.com/chromiumos/third_party/binutils/+/refs/heads/master/gas/testsuite/gas/ppc/vle.s).
 2021-04-12 03:18:42 -06:00
Robert Xiao 049bb2a3db
Update tricore2.idx to match available docs 
The existing page numbers on tricore2.idx appear to have been obtained by adding 49 to the numbers in the index of the [documentation file](https://www.infineon.com/dgdl/Infineon-TC2xx_Architecture_vol2-UM-v01_00-EN.pdf?fileId=5546d46269bda8df0169ca1bf33124a8); however, the page numbers in the index are actually wrong, and several instructions aren't actually documented in that manual despite appearing in the index.

By scraping the bookmarks and links directly from the PDF, a corrected set of page numbers has been generated, excluding undocumented instructions.
 2021-04-12 03:15:33 -06:00
Robert Xiao 0c2dd93500
Update reference for VMX instructions 
The VMX instructions are not in `AMD64_128-bit_SSE5_Instructions.pdf`; replace with a reference to the VMX instruction guide instead.
 2021-04-12 00:59:15 -06:00
ghidorahrex 6eb6bde3f4 Simplified PIC24 return instruction semantics. 2021-04-09 14:17:40 -04:00
ghidra1 b3e90569fd Merge remote-tracking branch 'origin/GP-513_JoinedReturnValue' 2021-04-02 18:15:22 -04:00
ghidra1 8e4be06649 Merge branch 'GP-798_ghidorahrex_PR-2855_gtackett_pic24_tblpag_psvpag' 
(Closes #2855)
 2021-04-02 18:03:19 -04:00
ghidra1 086922c254 Merge remote-tracking branch 
'origin/GP-818_ghidorahrex_PR-2447_cmasupra_xra_8085' (Closes #2447)
 2021-04-02 17:41:34 -04:00
ghidorahrex 8ca49b2cac Re-ordered sleigh instructions in x86 to correct addressing mode issues. 2021-04-01 10:46:35 -04:00
ghidra1 9a8228467b Merge remote-tracking branch 
'origin/GP-703_ghidorahrex_PPC_regression_fix--SQUASHED'
 2021-03-26 16:01:32 -04:00
ghidorahrex 6afdbcfc86 GP-703 improved various return from interrupt instruction semantics for PowerPC 2021-03-26 15:58:44 -04:00
VGKintsugi 27ad2f4b8c
SuperH: simplify div1 logic 
asdf-prime's modifications to div1 instruction. See PR: https://github.com/NationalSecurityAgency/ghidra/pull/2478
 2021-03-25 02:38:21 -04:00
VGKintsugi f1fc3a29ca
SuperH: Delay slot fix for bf/s and and bt/s 
Code now caches the value of the $(T_FLAG) before executing the delay slot. Previously the instruction executed in delay slot could potentially change the value of $(T_FLAG) and thereby resulting in incorrect behavior. Credit to Slinga and Waterfuell from SegaXtreme for reporting the issue.
 2021-03-25 02:08:22 -04:00
James 75e96f6128 GP_799-James-x64_vector_op_fixes 2021-03-24 19:44:34 +00:00
caheckman 872cd724cb Split out BE and LE cspec for MIPS 2021-03-24 13:23:04 -04:00
ghidra1 966e80469d Merge remote-tracking branch 'origin/GP-703_ghidorahrex_ppc_vle_interrupt_returns' 2021-03-23 15:22:43 -04:00
ghidorahrex ffa67eb295 Refactored interrupt return instructions for PPC 2021-03-23 11:08:56 -04:00
gtackett 0cc1568871
Fix for #2844 re. addresses of TBLPAG and PSVPAG 2021-03-18 09:57:45 -04:00
ghidra1 d377d90e14 Merge remote-tracking branch 'origin/patch' 
Conflicts:
	Ghidra/Features/GraphServices/certification.manifest
 2021-03-17 19:38:50 -04:00
ghidra1 74ef9b86c7 Merge remote-tracking branch 
'origin/GP-761_ghidorahrex_PR-2451_JeffmeisterJ_fix_arm_crn1_coproc_regs'
(Closes #2451)
 2021-03-17 19:22:47 -04:00
ghidra1 82cecede95 Merge remote-tracking branch 
'origin/GP-766_ghidorahrex_PR-2829_fmagin_fix_insX_rep' (Closes #2829)
 2021-03-17 19:21:41 -04:00
ghidra1 162f203395 Updated certification headers 2021-03-17 18:22:50 -04:00
ghidra1 0bf88594c9 Merge remote-tracking branch 
'origin/GP-748_ghidorahrex_superh4_fix_bad_dummy_exports' (Closes #2638)
 2021-03-15 17:50:36 -04:00
Florian Magin 511ab0b132 Fix INSx.REP instruction 
Co-authored-by: Sam Lerner <lerner98@gmail.com>
 2021-03-11 16:28:03 +01:00
ghidra1 399dd9484f Merge remote-tracking branch 
'origin/GP-758_ghidorahrex_PR-2651_miek_68000_byte_SP' (Closes #1709,
Closes #2651)
 2021-03-10 12:58:12 -05:00
ghidra1 ab26ac95bd Merge remote-tracking branch 'origin/GP-744_ghidorahrex_x86_movups_fix' 
(Closes #2789)
 2021-03-10 12:27:10 -05:00
ghidra1 9028a3122c Merge remote-tracking branch 
'origin/GP-736_ghidorahrex_PR-2754_miek_68000_fmove_packed_dynamic'
(Closes #2754)
 2021-03-09 09:07:08 -05:00
ghidra1 478b8bdaec Merge remote-tracking branch 
'origin/GP-735_ghidorahrex_PR-2750_PhysSong_arm_vmrs_fix' (Closes #2750)
 2021-03-09 09:04:09 -05:00
ghidorahrex b5f950bb2c Removed unneeded SuperH4 dummy exports 2021-03-04 11:55:11 -05:00
ghidorahrex 9a37a3a19a Corrected processor ordering for movups pcode 2021-03-03 07:55:44 -05:00
ghidra1 bd8d076a55 GP-710 Added register symbol processing to ELF PIC30 import processing. 
Improved code unit operand format to render memory register name when no
reference is present.
 2021-02-25 19:08:18 -05:00
ghidra1 a60b89cd86 GP-710 Added support for additional PIC30 ELF relocations (closes #2792) 2021-02-25 19:08:04 -05:00
ghidra1 3fadc49006 Merge branch 'patch' 
Conflicts:
	Ghidra/Features/GnuDemangler/src/main/java/ghidra/app/util/demangler/gnu/GnuDemanglerParser.java
 2021-02-25 19:07:31 -05:00
ghidra1 cefc2e52ad Revert "GP-710 Added support for additional PIC30 ELF relocations (closes #2792)" 
This reverts commit 9c1fed6a13.
 2021-02-25 19:05:05 -05:00
ghidra1 ce910a1112 Revert "GP-710 Added register symbol processing to ELF PIC30 import processing. Improved code unit operand format to render memory register name when no reference is present." 
This reverts commit c545a6fb5a.
 2021-02-25 19:04:33 -05:00
ghidra1 ad7cc85908 Merge remote-tracking branch 'origin/patch' 2021-02-23 16:28:18 -05:00
ghidra1 c545a6fb5a GP-710 Added register symbol processing to ELF PIC30 import processing. 
Improved code unit operand format to render memory register name when no
reference is present.
 2021-02-23 16:06:45 -05:00
ghidra1 8e90dfda7e Merge remote-tracking branch 'origin/patch' 2021-02-23 12:56:10 -05:00
ghidra1 9c1fed6a13 GP-710 Added support for additional PIC30 ELF relocations (closes #2792) 2021-02-23 12:48:27 -05:00
ghidra1 890fb55378 Merge remote-tracking branch 'origin/GP-0_ryammkurtz_PR-1783_astrelsky_DataLanguageDescription' 2021-02-16 14:33:32 -05:00
ghidra1 d257602096 Merge remote-tracking branch 'origin/GP-0_ryanmkurtz_PR-1756_LorenzNickel_spelling' 2021-02-16 14:32:18 -05:00
Mike Walters 4904a0e7b5 68000: fix disassembly of fmove with dynamic k-factor 2021-02-13 02:20:52 +00:00
Hyunjin Song 6d97ccee64
Fix ARM Neon VMRS instruction for little endian 2021-02-12 13:50:37 +09:00
ghidra1 9f56e3169b GP-662 added ELF support for process-specific symbol resolution 2021-02-04 15:44:19 -05:00
ghidra1 d91dd11fdc GP-0 change PowerPC R_PPC_COPY and R_PPC64_COPY ELF relocation failure 
to a warning
 2021-02-03 10:35:25 -05:00
ghidra1 2fd92e6f23 Merge remote-tracking branch 'origin/patch' 2021-02-02 19:42:19 -05:00
emteere 3426df3ba5 GP-655_emteere Added CFINV and defined local temps, also cleaned up some 
unnecessary sub-pieces
 2021-02-02 19:21:51 +00:00
ghidra1 c728a5323e Merge remote-tracking branch 'origin/patch' 2021-02-01 11:13:24 -05:00
ghidra1 bb665bda63 GP-651 add support for ELF relocation R_X86_64_IRELATIVE 2021-02-01 10:49:49 -05:00
ghidra1 424eac6319 Merge remote-tracking branch 'origin/patch' 2021-01-26 12:14:56 -05:00
emteere 5338bb74b7 GP-627_emteere Added missing VMUL F16 variants 2021-01-26 12:09:43 -05:00
Hyunjin Song 6e7239f43a Fix some ARM NEON vmul opcodes 2021-01-26 12:09:21 -05:00
ghidra1 4129d08611 Merge remote-tracking branch 'origin/patch' 2021-01-25 15:47:43 -05:00
ghidra1 32ae57e312 Merge remote-tracking branch 
'origin/GP-33_emteere_PR-1766_mumbel_mips-rfe' into patch
 2021-01-25 15:45:45 -05:00
emteere d7a1085619 GP-33_emteere Updated comment, read Status reg only once 2021-01-25 15:21:47 -05:00
Mike Walters ad1c5d7819 68000: fix SP postincrement/predecrement with byte operands 
When the address register is the stack pointer and the operand size is
byte, the address is incremented/decremented by two to keep the stack
pointer aligned to a word boundary.
[M68000 Family Programmer’s Reference Manual; 2.2.4 & 2.2.5]

fixes #1709
 2021-01-15 19:24:45 +00:00
ghidra1 5890b88f56 Certification update 2020-12-30 09:44:29 -05:00
ghidra1 70972b33a8 Merge remote-tracking branch 'origin/patch' 2020-12-30 09:41:12 -05:00
ghidra1 1c70e034b3 Merge branch 'GP-556_ghidra1_PR-1610_bstreiff_DWARF_m68k_SVR4' 2020-12-30 09:39:24 -05:00
Matt Ihlenfield 96fe213bfd GP-555 Added support for R_ARM_MOVW_ABS_NC and R_ARM_MOVT_ABS elf 
relocations
 2020-12-30 09:21:51 -05:00
reedmideke e51639b095 Fix #2559 by removing invalid variant of vst4 2020-12-29 12:05:50 -05:00
emteere 6bce112db6 GP-548 fixed v850 JUMP register relative instruction 2020-12-29 09:08:07 -05:00
mumbel 31c466c83e Bad long size (and alignment) 2020-12-27 22:29:04 -06:00
ghidra1 5bffb5c6ed Merge remote-tracking branch 'origin/GP-389_ArmSwitchFixup' into patch 2020-12-14 12:35:04 -05:00
ghidra1 9832f58435 GP-512 corrected ARM 8-byte return storage in cspecs 2020-12-14 10:20:24 -05:00
ghidra1 64e0ef10d7 GT-3657 corrected ARM pcodeop spelling of 
coproc_moveto_Identification_registers
 2020-12-08 14:21:39 -05:00
ghidra1 d7dbcfebf5 GP-420 relaxed memory block naming restrictions and eliminated throwing of DuplicateNameException from memory block API 2020-11-23 17:35:49 -05:00
caheckman 1f443a15b4 Fix to ARM switch function fixups 2020-11-13 17:15:11 -05:00
emteere 7bd149cb84 GP-0_emteere minor change to make SP unaffected on V850 2020-11-12 20:22:24 -05:00
Jeffrey 6b145561d1 Changed Non-Secure to NonSecure, because the dash breaks the build 2020-11-12 01:46:25 +01:00
Jeffrey 823887cf89 Added missing CRn == c1, op1 == 0 coproc registers 2020-11-12 01:21:30 +01:00
Jeffrey 865b156b08 Fixed ARM coproc regs for CRn == c1 2020-11-12 01:21:03 +01:00
cmasupra 6201b9bcdf
Update 8085.slaspec with "XRA M" or "XRA HL" 
This adds the instruction "XRA M" in addition to "XRA r", which already exists. "XRA M" is the Intel format, but the code being added will keep the Ghidra format of "XRA HL". Intel's MCS-80/85(tm) Family User's Manual from October 1979 indicates "XRA M" is a 1-byte instruction with value 0xAE.
 2020-11-09 15:59:11 -06:00
astrelsky afc647a28f Prevent silent AddressOutOfBoundsException in MipsAddressAnalyzer 2020-11-05 14:13:35 -05:00
Alexey Esaulenko c97f8007a0 Z80: fix CPIR / CPDR conditions 2020-11-03 18:59:20 -05:00
ghidra1 b9d16db00e Merge remote-tracking branch 'origin/GT-3654_ghidra1_ELF_R_ARM_PC24' into Ghidra_9.2 2020-11-03 16:46:10 -05:00
emteere b1e75e0d6f GP-358_emteere Minor RISV code review changes 2020-11-03 16:41:29 -05:00
mumbel 5fe0f16e10 c.fsw broken under double-precision 
if FP is 64, should still handle single precision
 2020-11-03 16:41:28 -05:00
mumbel a487f77918 Opinion fix 
Does not handle all the cases it can, add in size IMAFC and
generic cases for GC.
 2020-11-03 16:41:27 -05:00
mumbel c9ae8bdd8d Update to RISCV processor module 2020-11-03 16:41:26 -05:00
ghidra1 434b3bbd44 GT-3654 Corrected ELF R_ARM_PC24 processing 2020-11-03 14:06:06 -05:00
ghidra1 021fbf8025 GP-348 Added ELF RELR relocation support 2020-11-01 21:41:55 -05:00
ghidra1 d3950946e6 Merge remote-tracking branch 'origin/GP-343_AARCH64neon' into Ghidra_9.2 2020-10-29 18:55:15 -04:00
ghidra1 40a55b0d6b Merge remote-tracking branch 
'origin/GP-181_James_x64_zero_extend_32_bit_results' into Ghidra_9.2
 2020-10-29 18:52:48 -04:00
caheckman 1022be3a22 eliminate rest of simd_address_at 2020-10-28 11:38:29 -04:00
caheckman a4f5472e94 Refactor AARCH64 neon 2020-10-28 11:38:26 -04:00
ghidra1 6107f29a95 GP-302 corrected issue affected ELF PLTGOT bounds determination. 
Corrected various pointer and data related issues
 2020-10-23 18:57:11 -04:00
ghidra1 b83f327e47 Added direct references to MemoryBlock.EXTERNAL_BLOCK_NAME instead of 
hard-coded string
 2020-10-08 14:04:20 -04:00
emteere a1a49b204c GP-183_emteere split cspec for SH2A which includes floating point 
registers.  Couldn't use superh.cspec. 1/2 don't have these floating
point registers
 2020-10-05 17:34:55 -04:00
emteere 42b8eb3096 GT-3394_emteere fix for wrong store/load register list in Thumb mode for 
VLDMIA/VSTMIA instructions
 2020-10-02 15:24:00 -04:00
ghidra1 2a62adfa96 Merge remote-tracking branch 'origin/GP-183__PR-2218_esaulenka_sh2-float' into Ghidra_9.2 2020-10-02 14:56:05 -04:00
James 02205b7651 GP-181 corrected numerous zero extension issues 2020-10-02 10:31:03 -04:00
ghidra1 6927b8e0f5 Corrected certification issues 2020-10-01 14:32:01 -04:00
Alexey Esaulenko 624d0f94d7 Infineon Tricore: simplify st.t instruction 2020-10-01 19:04:16 +03:00
ghidra1 39ef49d1d1 Merge remote-tracking branch 'origin/GP-49_external_disassembly_upgrade--SQUASHED' into Ghidra_9.2 2020-09-29 10:23:16 -04:00
ghidra1 356ea446c7 GP-49 external disassembly field can now switch based upon context (implemented for ARM/Thumb) 2020-09-29 10:22:46 -04:00
ghidra1 0cdc722921 Revert analyzer default enablement change 2020-09-26 08:53:30 -04:00
ghidra1 226e1952cf Merge remote-tracking branch 'origin/GT-3594_ghidorahrex_PR-1593_czietz_m68000_usp' 2020-09-24 10:41:06 -04:00
ghidra1 558844aaa9 Merge remote-tracking branch 'origin/GT-3643_ghidorahrex_arm_ldrt_bitpattern' 2020-09-22 10:26:00 -04:00
emteere a7d5e983b7 GT_3394_emteere minor fix for Arm v6 with VFPv2 but not VFPv3. Fix 
subconstructor matching for reg d0
 2020-09-21 21:20:00 -04:00
ghidra1 3e57a90f05 Merge remote-tracking branch 'origin/GT-3052_ghidorahrex_M8C' 2020-09-21 14:21:38 -04:00
ghidra1 69487edc12 Merge remote-tracking branch 
'origin/GT-3394_ghidorahrex_arm_instruction_fixup'

Conflicts:
	Ghidra/Features/Base/certification.manifest
 2020-09-21 14:06:00 -04:00
ghidra1 ef1a39fe23 Merge remote-tracking branch 'origin/GP-177_ghidra1_StickyAnalyzerEnablement' 2020-09-18 16:28:37 -04:00
ghidra1 c62adccafb Merge remote-tracking branch 'origin/GP-124_emteere_AARCH64_v8.5' 2020-09-18 16:28:05 -04:00
ghidra1 4ecf402341 Merge remote-tracking branch 'origin/GP-58_caheckman_RiscvDecodeStates' 2020-09-18 16:27:43 -04:00
ghidra1 952e7225fa Corrected certifications 2020-09-18 16:26:40 -04:00
Dan 8aba96d762 GP-134: Fixed SleighCompileRegressionTest (typo in toy.sinc) 2020-09-18 09:23:04 -04:00
Dan 8cc2ce4eb4 GP-134: Fixed typo in toy.sinc. Fixed ExternalFunctionMergeManagerTest. 2020-09-18 08:34:46 -04:00
emteere 9e0c6b9372 GT-3394 Fixing UDF instruction flow 2020-09-17 21:28:41 -04:00
ghidorahrex 3778831902 GT-3394: Created ARM v6 pspec 2020-09-17 21:28:40 -04:00
ghidorahrex ea6cfcd08c Revert "GT-3394: Fixed register definitions in VLDM/VSTM instructions" 
This reverts commit 0858a9140d0f7c9c7e1f2e412d3c19a6087e5d1e.
 2020-09-17 21:28:39 -04:00
ghidorahrex cfcfff0afc GT-3394: Fixed register definitions in VLDM/VSTM instructions 2020-09-17 21:25:50 -04:00
ghidorahrex 389387c9d3 GT-3394: Fixed ARM instruction issues 
- Added missing THUMB instruction variants
- Corrected VFPv2/VFPv3/SIMD errors
 2020-09-17 21:21:43 -04:00
ghidra1 0df36d17a3 GP-177 allow changes to Stack and PDB analyzer enablement to be retained 
as a new default enablement
 2020-09-17 19:40:35 -04:00
emteere e910b7260e GP-124 Fixed BE register zero filling, re-indexed for latest manual, add 
missing V8.6, 8.5, and 8.4 instructions
 2020-09-17 14:23:22 -04:00
ghidra1 02e017f507 Merge remote-tracking branch 'origin/GT-2567_ARM_neon_vstm' 2020-09-17 12:00:45 -04:00
tellowkrinkle cbca52f9ae Longs are 64 bits in AARCH64 GCC/Clang 2020-09-17 11:49:29 -04:00
Dan ae83715648 Re-adding toy subregisters after fixes applied to merge of GP-134. 2020-09-17 08:21:48 -04:00
emteere ad96867b74 GT-2567 fixed vldm*/vstm* semantics 2020-09-16 21:30:12 -04:00
ghidra1 40b747acee Corrected toy language compile issues 2020-09-16 14:29:10 -04:00
ghidravore b23e3a9047 Merge remote-tracking branch 'origin/GP-134_DebuggerMainlineChanges--SQUASHED' 2020-09-16 13:21:56 -04:00
ghidravore 724df5a44c GP-134: Mainline changes cherry-picked from Debugger branch 2020-09-16 13:20:45 -04:00
ghidra1 f3b4e6de16 GP-164 Added ELF ARM relocation R_ARM_PREL31 and corrected issue with 
R_ARM_ABS32 relocation.
Fixes #2261, Fixes #2276
 2020-09-16 12:48:40 -04:00
ghidra1 da92b68bcd GP-164 Corrected ELF ARM R_ARM_REL32 (type 3) relocation processing 2020-09-15 20:12:41 -04:00
emteere 82f58c22d2 GT-2567 adding missing neon instructions, correcting shift calculation 
of several neon instructions, upping version number due to
sub-constructor split
 2020-09-14 21:35:34 -04:00
emteere 93473d3282 GT-2567 fixed long standing issue with pointer source register 2020-09-14 20:50:39 -04:00
ghidorahrex 169b23b1e0 GT-2567: implemented vstmia/db and vldmia/db ARM neon instructions 2020-09-14 20:50:38 -04:00
ghidra1 04594f770b Merge remote-tracking branch 'origin/GP-68_James_arm_thumb_fixes' 2020-09-11 19:45:35 -04:00
ghidra1 85073f4c46 Merge remote-tracking branch 'origin/GP-64_ghizard_Partial_Clang_Windows_Support' 2020-09-11 19:44:58 -04:00
emteere e500396bca Updates for missing v8.5 and v8.6, more changes needed 2020-09-11 19:34:39 -04:00
James 6707536818 arch64 add with carry fixes 2020-09-11 19:34:10 -04:00
emteere c2632f16a0 GP-124_emteere_AARCH64_v8.5 first cut at 8.5 instruction extensions 2020-09-11 19:33:47 -04:00
James 5e40f00351 arm fixes 2020-09-01 21:21:29 -04:00
ghidra1 36e9e6dd66 Merge remote-tracking branch 'origin/GT-2909_emteere_Xmega' 2020-08-28 11:01:26 -04:00
emteere 599dc0a1d1 GT-2909_emteere_Xmega made memory access registers non-volatile so 
references could be made
 2020-08-27 14:00:48 -04:00
emteere 6bbcbf0277 GT-2909_emteere_Xmega minor typo changes 2020-08-25 11:39:34 -04:00
James 31a377b6d0 fixing ARMTHUMBinstructions.sinc 2020-08-25 09:42:47 -04:00
Alexey Esaulenko 90c14006ca SH2 float calling conventions 2020-08-21 11:48:44 +03:00
Alexey Esaulenko a12a0c19de SH2 float substract fix 2020-08-21 11:20:01 +03:00
ghizard 0013025a40 GP-64 Partial Clang-for-Win support: PeLoader, opinion/ldefs, fix some 
analyzers and their helpers and tests
 2020-08-10 12:23:55 -04:00
emteere 99e385da6a GT-2909 refactored IO_START implementation, added load/store of real 
flags register
 2020-08-05 13:47:51 -04:00
ghidravore e76329979a Merge remote-tracking branch 'origin/caheckman_JavaPcodeInjection' 2020-08-03 14:03:01 -04:00
ghidravore 513467b150 Merge remote-tracking branch 'origin/caheckman_RenameRegParam' 2020-08-03 13:53:52 -04:00
caheckman 2e9fdb7de8 Adjustment to RISCV decode states 2020-08-03 13:44:19 -04:00
ghidorahrex 77212ed745 Merge remote-tracking branch 
'origin/GT-54_ghidorahrex_PR-2120_ahroach_risc-v-jmp-pcode-fix'

Fixes #2120
 2020-07-31 10:51:53 -04:00
caheckman 45b43b18c3 Remove deprecated PcodeTextEmitter 2020-07-30 16:56:36 -04:00
caheckman 004a99bb87 Attach handling of "this" to ProtoParameter 2020-07-30 12:22:21 -04:00
caheckman 93039d3958 Synchronize access to ClassFileAnalysisState 2020-07-29 17:08:41 -04:00
caheckman 9c2ce9b395 Convert java InjectPayload 2020-07-29 16:00:07 -04:00
ghidra1 81f5776555 GT-2909 AVR8 ELF import and pcode test improvements 2020-07-29 14:29:46 -04:00
caheckman 2d690404fe InvokeMethodsTest passing 2020-07-29 14:02:36 -04:00
caheckman f4d25ccebb InvokeMethodsTest passes 2020-07-29 13:39:20 -04:00
caheckman 822ea1a376 ReferenceMethodsTest pass 2020-07-29 12:49:16 -04:00
caheckman 5327985d0b ReferenceMethods refactor 2020-07-29 12:18:46 -04:00
caheckman ad34d91f9b replacement for PcodeTextEmitter 2020-07-29 10:31:33 -04:00
ghidorahrex 6677daca41 Merge remote-tracking branch 'origin/GP-44_x64_sleigh_fixes' 2020-07-29 10:15:50 -04:00
James 19f8137808 GP-44 bit manipulation/shift/rotate fixes 2020-07-28 16:43:38 -04:00
emteere 1f8ced9b8d GT-2909_emteere fixing pcodeunit tests from removal of register 2020-07-24 17:47:03 -04:00
emteere 2a8a3d6ba6 GT-2909_emteere_Xmega fixed comment 2020-07-24 17:47:02 -04:00
emteere 0f8bd6b036 GT-2909_emteere_Xmega added xmega processor and missing pcode 2020-07-24 17:47:01 -04:00
Octocontrabass c9fcb5efe7
SuperH: correct rotr instruction 2020-07-23 16:05:36 -07:00
Austin Roach 688ed5e00d RISC-V j/jr semantics: use goto instead of call 
In the RISC-V binaries that I've been looking at, the j and jr
instructions have been used exclusively for intraprocedural control flow
transfers, where the function-call hinting associated with the CALL
p-code op leads to nasty side effects in the control flow
reconstruction.
 2020-07-20 20:48:37 -04:00
ghidra1 a7ab44fc6e Merge branch 'GT-0_ghidra1_PR-1891_agatti_Pic17' 2020-07-16 17:08:33 -04:00
ghidorahrex 0d180ad357 Merge remote-tracking branch 
'origin/GT-3426_ghidorahrex_PR-1383_agatti_cp1600'

Fixes #1383
 2020-07-16 14:11:26 -04:00
ghidorahrex b7481d2088 Merge remote-tracking branch 
'origin/GT-3524_ghidorahrex_PR-1450_mumbel_riscpatt'

Fixes #1450
 2020-07-16 14:09:41 -04:00
ghidorahrex 16e98bfea6 GT-3643: Corrected ARM ldrt instruction bit-pattern 2020-07-16 10:55:58 -04:00
WorksButNotTested b3b7bab4ca Added secondary selectors to ARM opinion file for correctly identifying 
ARMBE8 binaries
 2020-07-14 16:12:02 -04:00
ghidorahrex 60cd19701d GT-3426: Added certification 2020-07-14 15:54:57 -04:00
ghidorahrex cde035d8b2 Merge remote-tracking branch 
'origin/GT-3641_ghidorahrex_PR-2005_simeonpilgrim_arm_STREX_fix'

Fixes #2005, fixes #2010
 2020-07-14 14:27:43 -04:00
ghidorahrex 53a4b62726 Merge remote-tracking branch 
'origin/GP-34_ghidorahrex_PR-2088_bgK_6502-cmp-carry-flag'

Fixes #2088
 2020-07-14 09:12:33 -04:00
WorksButNotTested 556710d261 #1494: Fix incorrect handling of relocations for ARM BE8 binaries 2020-07-13 18:35:22 -04:00
Bastien Bouclet fe90271558 Fix the carry flag value for the CMP, CPX and CPY 6502 instructions 
The CPU manual states "the carry flag is set when the value in memory is
less than or equal to the accumulator, reset when it is greater than the
accumulator".
 2020-07-12 14:16:57 +02:00
ghidra1 9af174f9fe Merge remote-tracking branch 'origin/caheckman_BaseSpaceID' 2020-07-01 16:14:23 -04:00
ghidra1 8ac353572b Corrected sleigh compile failure for V850 2020-07-01 10:26:51 -04:00
ghidorahrex c5a31bb129 Merge remote-tracking branch 
'origin/GP-23_ghidorahrex_PR-1802_vvasseur_fix_teq_in_arm_thumb'

Fixes #1802
 2020-06-30 15:07:29 -04:00
ghidorahrex ae0209eede Merge remote-tracking branch 'origin/GP-18' 2020-06-30 14:10:42 -04:00
ghidra1 b8dde7b4c8 Corrected sleigh compile issues for V850 2020-06-30 13:43:05 -04:00
James 3e1954ebe9 GP-18 updated ia.sinc 2020-06-30 10:34:57 -04:00
James 1ed4407e3d fixes to ia.sinc 2020-06-29 14:58:26 -04:00
emteere 0bfcb5b8cd Merge remote-tracking branch 'origin/GT-3523_emteere_PR-1430_Aleckaj_master' 2020-06-26 15:36:47 -04:00
emteere 2a30ec7112 GT-3523_emteere_PR-1430_Alackaj_master fixing patterns file and review 
for merge into master
 2020-06-26 14:54:05 -04:00
ghidra1 c7cc11a18e Merge branch 'GT-0_ghidra1_PR-1761_Random06457_ELF_MIPS_Options_Bug' 2020-06-26 11:54:00 -04:00
Simeon Pilgrim 632a768cf3 copy hasExclusiveAccess pattern into ARM STREX instruction to be the same as the THUMB and STREXn instructions 2020-06-19 09:38:04 +12:00
caheckman 93c8171ffa Refactor getBaseSpaceID -> getSpaceID 2020-05-22 18:57:12 -04:00
emteere 7a13061e4a GP-10_emteere adding missing get_pc_thunk.as/si 2020-05-22 15:39:00 -04:00
ghidravore 875eed4c3b Merge remote-tracking branch 'origin/caheckman_recentBranches' 2020-05-22 13:29:33 -04:00
Alessandro Gatti a9663958e1 Handle all PCLATH modification cases. 2020-05-21 15:03:19 +02:00
heinrich5991 a3b65be841 Autodetect the ___chkstk_ms symbol 
Fixes #1888.
 2020-05-21 01:07:08 +02:00
ghidra1 305a1ddf98 Merge branch 'ghidra1_PIC30_ElfImportFixes' 2020-05-14 16:02:55 -04:00
ghidra1 251e14562d PIC24/30/33 corrections and ELF import improvements for Harvard 
Architecture
 2020-05-14 15:29:52 -04:00
Alessandro Gatti 165334c9c9 Use just one memory access for SDBD reads/writes. 2020-05-13 22:25:31 +02:00
caheckman b3bd637d99 Filling in some vector instructions that were causing "Overlapping input 
varnodes"
 2020-05-12 14:08:31 -04:00
emteere 44037991d2 GT-3393_ghidorahrex_ARM_missing_spaces minor format issue in ARMThumb 
from GT-3393 changes
 2020-05-11 17:08:54 -04:00
Alessandro Gatti 36c16b2cde Address review isues. 2020-05-09 23:08:15 +02:00
Alessandro Gatti 551154e32f Add R7 handling and remaining synthetic opcodes. 2020-05-07 23:18:18 +02:00
Alessandro Gatti 07cc606f7c Add TSTR synthetic opcode. 2020-05-07 04:18:20 +02:00
Alessandro Gatti ee59487205 Add PSHR and PULR synthetic opcodes. 2020-05-07 04:18:19 +02:00
Alessandro Gatti 3baebe2d38 Prepend the appropriate marker to number literals. 2020-05-07 04:18:19 +02:00
Alessandro Gatti 9da10a6b7e Fix backwards relative jumps. 2020-05-07 04:18:19 +02:00
Alessandro Gatti 941f9e15c9 Reverse jump condition check. 2020-05-07 04:18:19 +02:00
Alessandro Gatti 8e9940c497 Remove D flag, it is a context variable now. 2020-05-07 04:18:19 +02:00
Alessandro Gatti 6184f58475 Use one single entry for conditional opcodes. 2020-05-07 04:18:19 +02:00
Alessandro Gatti c72e4bc98b Use noflow in context entry. 2020-05-07 04:18:19 +02:00
Alessandro Gatti 59bf667520 Fix review issues. 2020-05-07 04:18:19 +02:00
Alessandro Gatti 51d73bd395 CP1600-series processor support. 2020-05-07 04:18:18 +02:00
Valentin Vasseur eed394f8a3 ARM: Fix sleigh description of teq in Thumb mode 
teq performs a bitwise EXCLUSIVE or, not an inclusive or. (See section
A8.8.238 of the ARMv7 reference manual.)
 2020-04-26 01:52:01 +02:00
astrelsky 00034b6fb2
Fixed Raw Data big endian "processor" description 2020-04-16 21:17:48 -04:00
mumbel 734c945f6d MIPS missing rfe instruction 2020-04-13 15:30:21 -05:00
Random 4bed300b33 Fix a bug when parsing the elf SHT_MIPS_OPTIONS section 2020-04-13 19:09:32 +02:00
Lorenz Nickel 2535e606b8 Fix some typos within comments 2020-04-13 08:35:34 +02:00
Aleckaj cfc4c8c92c Added .opinion File by @HexRoman for the analyzeHeadless 2020-04-12 20:32:40 +02:00
ghidra1 3b05eada12 Merge remote-tracking branch 'origin/patch' 2020-03-27 12:30:34 -04:00
ghidra1 7c8d4257e0 Corrected PIC24 non-critical property key 2020-03-27 10:34:21 -04:00
ghidorahrex 0b5abaa7a7 Merge remote-tracking branch 
'origin/GT-3613_ghidorahrex_PR-1662_SamB_patch-1'

Fixes #1662
 2020-03-24 11:08:51 -04:00
Ryan Kurtz a5a03f7863 DyldCacheLoader now has an opinion for x86_64, allowing the standard 
macOS DYLD to be loaded.
 2020-03-23 13:56:45 -04:00
Samuel Bronson 060a4754cb
Update link in x86-64-win.cspec 
Just when you thought it was safe to link to MS docs ...
 2020-03-21 13:00:02 -04:00
ghidorahrex 9e568c9de3 Merge remote-tracking branch 'origin/GT-3276_ghidorahrex_avr8_flag_fixup' 2020-03-18 13:58:04 -04:00
ghidorahrex 4c7c3adf5a GT-3276: Fixed AVR8 addition/subtraction flag macros 2020-03-18 13:54:36 -04:00
ghidorahrex e8fab41a84 Merge remote-tracking branch 'origin/GT-3562_ghidorahrex_pic30' 2020-03-18 13:49:19 -04:00
ghidorahrex 707879af79 GT-3562: Updated pic24/pic30 idx and slaspec 2020-03-18 13:48:22 -04:00
ghidorahrex 68898fc5b8 Merge remote-tracking branch 'origin/GT-3576_AllocaProbe' 2020-03-18 13:46:07 -04:00
Brandon Streiff 5d57628b7f 68000: add m68k/SVR4 DWARF register mappings 2020-03-08 11:18:12 -05:00
ghidorahrex eed45cb311 Minor correction to AARCH64 to fix sleigh compile error. 2020-03-05 08:14:40 -05:00
ghidorahrex ddc63770b9 Merge remote-tracking branch 'origin/GT-3466_ghidorahrex_fix_export_const' 2020-03-04 14:26:27 -05:00
ghidorahrex f4ce8639e0 Merge remote-tracking branch 'origin/GT-3534_ghidorahrex_x86_AF_flag_inconsistencies' 2020-03-04 14:24:52 -05:00
Christian Zietz a25e48399e 68000: Rework fix for MOVE USP,x and MOVE x,USP 2020-03-04 16:51:19 +00:00
Christian Zietz 1cb3128623 Fix MOVE USP,x and MOVE x,USP opcodes 2020-03-03 20:11:08 +00:00
caheckman 05a773678a Adjust fixup for 64-bit alloca_probe implementations 2020-03-03 12:29:47 -05:00
ghidorahrex a621f6cefa GT-3573: Corrected SuperH rte instruction goto pcode 2020-03-02 13:12:49 -05:00
Aleckaj d37ef2a0c2 Added small changes from @esaulenka 2020-03-02 10:54:13 +01:00
mumbel ab6112c56e initial V850 patterns 2020-03-01 15:13:11 -06:00
Aleckaj f317ada6a8 Macros and cspec fixes 2020-02-24 20:28:58 +01:00
ghidorahrex 0ec0e703b3 Merge remote-tracking branch 'origin/GT-3393_ghidorahrex_ARM_missing_spaces' 2020-02-24 13:58:56 -05:00
ghidorahrex 89f1aa9574 Merge remote-tracking branch 
'origin/GT-3529_ghidorahrex_cr16c_abs20_fix'

Fixes #1518
 2020-02-24 13:54:57 -05:00
Aleckaj 798c94f36a Minor changes with help of @GhidorahRex 2020-02-21 09:33:12 +01:00
ghidra1 3c99e1063c Corrected RISCV language files which need blank line at end 2020-02-20 14:17:31 -05:00
ghidorahrex 322fb41a2c Merge remote-tracking branch 'origin/GT-3278_ghidorahrex_xgate_ROR' 2020-02-19 11:54:40 -05:00
ghidorahrex cba214a852 GT-3529: Updated language minor version number. 2020-02-19 11:12:04 -05:00
Aleckaj ddbbafaf5c adjusted .cspec-File 2020-02-19 09:43:42 +01:00
ghidorahrex 9faf39baed Fixed sleighCompiler test failures with riscv. 2020-02-18 14:43:18 -05:00
Aleckaj 8f3cf0d2dc Improved code with the help of @GhidorahRex 2020-02-17 16:30:15 +01:00
Alessandro Gatti 06490144dd Generalize 6502 processor spec file. 2020-02-13 18:19:06 +01:00
ghidorahrex 3c8f2bdeff Merge remote-tracking branch 'origin/GT-933_ghidorahrex_correct_atmega256_pspec' 2020-02-13 08:06:45 -05:00
ghidorahrex 2d69b43bd1 GT-3393: Fixed formatting for Ldlist in arm thumb 2020-02-12 07:36:18 -05:00
ghidorahrex 222b42a76b GT-3534: Removed AF flag setting in add/sub flags when not being set 
elsewhere
 2020-02-11 11:41:27 -05:00
ghidorahrex dcd5296041 GT-933: Code review fixes for atmega SP memory addresses in .pspec 2020-02-07 14:55:16 -05:00
ghidorahrex b06ca0c971 GT-3466: fixed exporting const local vars in avr32 2020-02-07 13:32:34 -05:00
ghidorahrex 02319781b6 GT-3466 Fixed export of local variables as constants 2020-02-07 12:07:26 -05:00
ghidorahrex 67631a27ef GT-3524: Certifying riscv pattern files. 2020-02-06 10:40:40 -05:00
ghidorahrex fda8cf924e GT-3529: Corrected cr16c.sinc abs20 subconstructor address mapping 2020-02-06 07:40:26 -05:00
ghidra1 0d641458ce Merge remote-tracking branch 'origin/patch' 2020-02-05 14:04:07 -05:00
ghidorahrex 4c31ac66ce GT-3489 Updated x86.idx with latest AMD and Intel instruction set 
manuals
 2020-02-05 13:38:11 -05:00
ghidorahrex 0914d476ef Merge remote-tracking branch 'origin/GT_3299_ghidorahrex_fix_negative_stackshift' 2020-02-05 09:38:41 -05:00
Benjamin Levy 74fae2f644 Merge branch 'master' of 
https://github.com/NationalSecurityAgency/ghidra into spell
 2020-01-29 11:37:23 -05:00
ghidorahrex 5ea27f70e9 GT-3299: Corrected stackshift and extrapop in cspecs. 2020-01-27 14:51:54 -05:00
ghidorahrex bc526da46f Merge remote-tracking branch 'origin/GT-3483_ghidorahrex_6x09_sleigh_error' 2020-01-27 07:28:18 -05:00
ghidorahrex 223e93f4d0 Merge remote-tracking branch 
'origin/GT-3467_ghidorahrex_tricore_storebit_bug'

Fixes #1463
 2020-01-27 07:21:38 -05:00
ghidorahrex 498abf1a31 Merge remote-tracking branch 'origin/GT-3420_ghidorahrex_arm_thumb_rsb' 
Fixes #1365
 2020-01-27 07:20:35 -05:00
ghidorahrex 292d802ab6 Merge remote-tracking branch 'origin/GT-3413_ghidorahrex_x86_32_rdrand' 2020-01-27 07:18:29 -05:00
ghidorahrex 5ff5426ffc Merge remote-tracking branch 'origin/GT-3408_ghidorahrex_arm_thumb_it_al_condition' 2020-01-27 07:17:57 -05:00
ghidorahrex 4c81e6837f Merge remote-tracking branch 'origin/GT-3429_ghidorahrex_m68000_move_overwrite' 2020-01-27 07:17:15 -05:00
Benjamin Levy a5efecea84 Fix spelling errors 2020-01-26 22:39:18 -05:00
ghidorahrex 6893491092 GT-3483: fixed sleigh error in 6x09 language spec. 2020-01-23 07:48:42 -05:00
ghidorahrex 98a56374fc Merge remote-tracking branch 
'origin/GT-3475_ghidorahrex_PR-1461_mumbel_tempwriteread'

Fixes #1461, fixes #1458
 2020-01-23 07:33:12 -05:00
ghidorahrex 428945c019 Merge remote-tracking branch 
'origin/GT-3469_ghidorahrex_PR-1321_lab313ru_m6800_roxr_roxl'

Fixes #1321, fixes #1320, fixes #1319
 2020-01-23 07:28:09 -05:00
mumbel dce6e9f6a8 Cleaning up warnings and errors, mostly looking for: 
temporary is written but not read in constructor
 2020-01-22 19:51:45 -06:00
ghidorahrex 463d5f2bf8 GT-3467: Corrected tricore store bit instruction 2020-01-21 10:39:15 -05:00
Aleckaj 5e660b8d9d Added Files for builder subsystem + little bugfixes 2020-01-21 13:22:46 +01:00
Aleckaj b356b40f9a Changed NOP Instruction 2020-01-19 17:28:15 +01:00
Aleckaj 392b38bf24 Added Manual and syncronised Code with @esaulenka 2020-01-18 11:27:28 +01:00
ghidorahrex 07e9853b97 Merge remote-tracking branch 
'origin/GT-3425_ghidorahrex_PR-1378_saruman9_fix_push_pop_seg'

Fixes #1378
 2020-01-17 12:30:06 -05:00
ghidorahrex 6ca9eafd1d GT-933: Corrected AVR8 atmega256 memory layout in .pspec 2020-01-17 11:38:46 -05:00
Aleckaj 946ef86935 Removed Whitespaces, Fixed some Floatissues, Fixed Divideproblems 2020-01-16 18:48:34 +01:00
ghidorahrex 79588bd3e5 Merge remote-tracking branch 
'origin/GT-3450_ghidorahrex_PR-1429_ahroach_fix-typo-AVR8.idx'

Fixes #1429
 2020-01-15 12:39:54 -05:00
ghidorahrex 5f1213ecd6 GT-3425: Accepting pull request 2020-01-15 06:37:57 -05:00
Aleckaj 9f6cbc8f39 Add V850E2M Architecture 2020-01-14 14:46:47 +01:00
Austin Roach 2dd6b50a38 Fix typo in AVR8.idx 2020-01-14 07:46:05 -05:00
mumbel 5fc98745bc initial patterns 2020-01-12 19:16:18 -06:00
gus c88faf567c Add Motorola 6809 Processor's manual index file. 2020-01-06 12:46:23 -03:00
gus be4df6d526 Add Motorola 6809 Processor's manual index file. 2020-01-06 12:43:20 -03:00
ghidorahrex c5f2fa286c GT-3429: Corrected issue with m68000 move instruction overwriting 
variables.
 2019-12-30 10:09:03 -05:00
Ryan Kurtz 26cab55a64 Merge remote-tracking branch 'origin/GT-3424_ghidorahrex_PR-1302_mumbel_tricoredvinit' 2019-12-23 10:36:27 -05:00
Ryan Kurtz 2c0d41b554 Merge remote-tracking branch 'origin/GT-3423_ghidorahrex_PR-1370_mumbel_x86_bt' 2019-12-23 10:27:56 -05:00
Ryan Kurtz 03c0872244 Merge remote-tracking branch 'origin/GT-3421_ghidorahrex_PR-872_andyhhp_x86-int' 2019-12-23 08:35:30 -05:00
saruman9 430baa01c6
Fix PUSH and POP instruction for segment registers in x86 
Create macros for push/pop instructions, which operates of segment registers. Add behaviour for
push/pop instructions, which operates of `FS` and `GS` segment registers in 64-bit mode.

For details see p. 1037 (`POP`) and p. 1163 (`PUSH`) of Intel's manual or open `Instruction Info...`
in the Ghidra.

Fix #1377.
 2019-12-22 00:51:22 +03:00
mumbel eafac1daa1 BT <r64>,<Reg64> used 32 bit instead of 64-bit modulo size 2019-12-20 14:58:10 -06:00
ghidorahrex f92528923d GT-3408: Corrected IT conditionals 2019-12-20 11:32:48 -05:00
ghidorahrex 7aa51fb572 GT-3420: Corrected RSB width modifier 2019-12-20 08:45:25 -05:00
ghidorahrex c2847fa9a4 GT-3413: Added rdrand/rdseed support to x86-32 2019-12-19 09:42:17 -05:00
ghidorahrex d47317a9f8 GT-3408: Included support of 'al' for IT instructions, generalized 
support for IT instructions and included the 'nv' condition although it
should never occur.
 2019-12-18 14:41:05 -05:00
ghidra1 8fbdec4eca Merge remote-tracking branch 'origin/patch' 2019-12-18 11:02:47 -05:00
emteere 5c1dcc6a1c emteere_MipsMultiThreadFix fix for potential multi threaded access to 
local class variable.
 2019-12-17 16:22:31 -05:00
Ryan Kurtz 2f1292b174 Merge remote-tracking branch 'origin/caheckman_x86parityflag' 2019-12-17 11:31:26 -05:00
emteere 67d774fa42 GT-3374_emteere several bugs and inneficiencies causing analysis to fail 
for programs with debug info
 2019-12-16 16:52:15 -05:00
Ryan Kurtz b22960b9f1 Merge remote-tracking branch 'origin/GT-3366_ghidorahrex_6805_bset_bug' 
(fixes #1307)
 2019-12-13 10:38:43 -05:00
ghidorahrex 2aee17ba31 GT-3299: Fixed stackshift/extrapop for 8051 and 6805. 2019-12-13 09:47:12 -05:00
ghidorahrex d30ba7c9b1 GT-3393 ARM parameter list spaces 
Corrected ARM subconstructors for spacing around register paramter
lists.
 2019-12-13 09:35:08 -05:00
ghidorahrex b8d6136505 GT-3366: code review fixes 2019-12-12 12:12:00 -05:00
Ryan Kurtz 3eb130123b Merge remote-tracking branch 'origin/GT-3389_ghidorahrex_PR-932_mumbel_riscv' 2019-12-11 14:21:08 -05:00
Ryan Kurtz 40069dcaab Merge remote-tracking branch 'origin/GT-3390_ghidorahrex_PR-1201_aladur_M6809Support' 2019-12-11 14:16:15 -05:00
ghidorahrex c7f6ea4fae GT-3390: Certifying 6809 processor specs 2019-12-10 16:10:48 -05:00
ghidorahrex b628a7e46f GT-3389: Certifying RISCV processor module. 2019-12-10 15:22:25 -05:00
mumbel d7e51ee515 RISC-V processor 
[riscv] Added context register for extensions

[riscv] missed a define in refactor

[riscv] got 100% on RV32IMC

[riscv] Add throw away script to generate SLEIGH

[riscv]

Fixes from SleighDevTools

- R4-type were using a bad bit pattern that broke the rs3 operand
- mul had a copy/paste typo that ignored the rs2 operand
- bad define guard for compressesed instruction
 2019-12-10 14:04:05 -06:00
Ryan Kurtz 21bd938845 Merge remote-tracking branch 'origin/GT-3379_ghidorahrex_PR-1286_mumbel_tricore_dvadj' 2019-12-10 09:03:51 -05:00
Ryan Kurtz 8170874fe6 Merge remote-tracking branch 'origin/GT-3380_ghidorahrex_PR-1295_roblabla_ptest' 2019-12-09 13:38:21 -05:00
Ryan Kurtz 4d8838a791 Merge remote-tracking branch 'origin/GT-3375_ghidorahrex_PR-1049_agatti_6502brk' 2019-12-09 10:00:28 -05:00
Vladimir Kononovich 876ee2881e
Fixed M68000 ROXR and ROXL 2019-12-07 21:12:33 +03:00
Alessandro Gatti 1d82dccbd2
Call the IRQ vector this time. 2019-12-07 00:36:09 +01:00
Ryan Kurtz 30140d88c7 Merge remote-tracking branch 'origin/GT-3368_ghidorahrex_PR-1277_lioncash_mul' 2019-12-04 13:58:08 -05:00
Ryan Kurtz 7e2185483b Merge remote-tracking branch 'origin/GT-3369_ghidorahrex_PR-1278_lioncash_vcvt' 2019-12-04 13:49:53 -05:00
Ryan Kurtz 2f62eb2e93 Merge remote-tracking branch 'origin/GT-3367_ghidorahrex_PR-1303_glamorous-noob_x86_salc' 2019-12-04 08:52:36 -05:00
ghidorahrex b5d5e32f78 GT-3366: Corrected 6805 pcode for CPX and SWI instructions 2019-12-03 13:03:37 -05:00
Raphaël Akladios bbf050a26e
Update the mnemonic to SALC and disallow it in b64 2019-12-03 15:48:01 +01:00
ghidorahrex ad7e6b2f05 GT-3366: Corrected pcode in 6805 BSET instruction 2019-12-03 08:43:06 -05:00
ghidorahrex d454912a87 GT-3278: Corrected XGATE ROR instruction semantics. 2019-12-02 13:37:50 -05:00
ghidorahrex 2272627787 GT-3311: Merged changes to operand sizing 2019-12-02 12:41:34 -05:00
Austin Roach 3bad6f753f AVR8: Improve operands for load/store instructions 
Currently, the operators for post-incremented or offset source operands
associated with various memory access instructions are separators
rather than components of the operand. As a result, inferred references
split the register and the operator when rendered in the listing, making
it easy to overlook the operator. For example:

lpm R0,Z=>DAT_code_000455+

This patch mimics logic already in place for the st and std
instructions, which include the post-increment operator or offset as
part of the operand. For example:

st X+=>DAT_mem_0100,R0
 2019-12-02 09:58:39 -05:00
Raphaël Akladios 304e3a56a3
x86: Add the "SETALC" instruction to SLEIGH specs 
The SETALC / SALC instruction is officially undocumented by Intel, and is currently missing form Ghidra.
A constructor for this instruction is added to the SLEIGH specification files according to the descriptions in these links:
http://www.rcollins.org/secrets/opcodes/SALC.html
http://ref.x86asm.net/coder32.html#xD6
 2019-12-02 04:52:22 +01:00
mumbel bdefdbb61a [tricore] Improved DVINIT instructions 
DVINIT instruction operate better using the even/odd pair for the
initialization instead of using the 64-bit register.

Reported by @esaulenka
 2019-12-01 10:55:46 -06:00
roblabla 6549d330f8 x86: Properly implement the PTEST instruction 2019-11-28 12:08:31 +00:00
caheckman d322303f59 Basic parity flag implementation for x86 2019-11-27 13:39:30 -05:00
Ryan Kurtz 8e4b143f58 Merge remote-tracking branch 'origin/GT-3339_x64_vector_ops' 2019-11-27 10:35:41 -05:00
James ac3361954f GT-3339 code review changes 2019-11-26 14:01:34 -05:00
ghidra1 ee25a7d0cc Merge remote-tracking branch 'origin/patch' 2019-11-26 12:37:20 -05:00
ghidra1 b7a3dff215 Merge remote-tracking branch 'origin/GT-3328_ghidra1_SleighArgs' into patch 2019-11-26 12:32:17 -05:00
mumbel 5c439e913e [tricore] Misuse of abs() turned into int_abs macro 2019-11-25 15:21:02 -06:00
mumbel cb298f224c Revert "[tricore] Fix usage of SLEIGH abs()" 
This reverts commit efde3ebaea.
 2019-11-25 14:20:38 -06:00
mumbel efde3ebaea [tricore] Fix usage of SLEIGH abs() 
Used abs() with integer, expecting integer results, which is incorrect

FLOAT_ABS - abs - Absolute value of v0 as floating point number.
 2019-11-25 10:08:06 -06:00
Roi Martin 7946ec5f62 AVR8: Fix lpm/elpm implementation in SLEIGH specification 
When Z & 0x1 == 1, the dereferenced data must be right-shifted 8 bits
before assigning val:1 to the target register.

When Z & 0x0 == 0, val:1 is assigned to the target register straight
away.

In short, we can reduce these conditions to:

	tmp:2 = *[code]:2 (ptr >> 1);
	val:2 = (tmp >> (8 * (Z & 0x1)));
	R0 = val:1;

NOTE: Author's original commit was modified to address conflicts and a necessary rebase. -ryanmkurtz
 2019-11-25 09:59:51 -05:00
Lioncash 9a5769979c ARM: Handle disassembly of VNMLA for F16/F32/F64 
These Sleigh constructors were acting as constructors for VNMLS, however
the constructors actually describe the bit encoding for VNMLA, which can
result in incorrect disassembly meaning.

This corrects this so that VNMLA instructions are properly disassembled
and also don't show up as generic CDP instructions.
 2019-11-24 05:25:15 -05:00
Lioncash 644f3c3449 ARM: Handle disassembly of conditional VNMLS for F32/F64 
Similarly with VNMUL, VNMLS is also able to execute with a condition
code for single-precision and double-precision floating point variants.

Like with the previous change, we can also amend the Sleigh constructor
so that it decodes properly (the condition code for a predictable
instruction is 0xE, not 0xF).

This fixes VNMLS instructions disassembling as generic CDP instructions,
making disassembly clearer.
 2019-11-24 03:01:22 -05:00
Lioncash 9670b81458 ARM: Handle disassembly of conditional VNMUL for F32/F64 
The single-precision and double-precision variants of VNMUL support
condition codes on them in ARM mode. We can amend the Sleigh
constructors to reflect this.

We can also amend the half-precision variant to reflect that the
condition code should be 0xE in terms of value. The ARMv8 architecture
reference manual states (at F6.1.148) that if a half-precision
instruction is present and does not have a condition code of 1110, then
the behavior is considered CONSTRAINED UNPREDICTABLE.

This fixes VNMUL instructions disassembling as generic CDP instructions,
making the disassembly much clearer.
 2019-11-24 03:00:48 -05:00
Lioncash 520f1c47d9 ARM: Correct Sleigh constructor for VCVT{R}<c>.S32.F32 
Bits 23-27 are defined with a bit encoding of 0b11101, not 0b11011 (See
section F6.1.60 within the ARMv8 reference manual or section A8.8.306
within the ARMv7 reference manual).

This makes conversions from floating-point registers to signed values
disassemble/decompile more properly and not as generic CDP instructions,
making decompilation a little more informative.
 2019-11-24 02:23:06 -05:00
ghidra1 9a470a9dc7 Merge remote-tracking branch 'origin/patch' 2019-11-22 16:50:54 -05:00
ghidra1 4fc507f711 GT-3349 Corrected ELF relocation fixups for R_MIPS_REL32, 
R_X86_64_RELATIVE and R_X86_64_RELATIVE64
 2019-11-22 16:49:24 -05:00
James 09745ce672 GT-3339 added pcode for x64 vector ops 2019-11-21 15:47:12 -05:00
Wesley Ceraso Prudencio 077b5788ab
Fixes the lvalue for movu.b and movu.w 
As with all other mov instructions, the second address is the lvalue, the one to receive the data.
For movu.b and movu.w the first address was receiving its own data.
 2019-11-21 08:22:52 -08:00
Ryan Kurtz 2f0b64a31a Merge remote-tracking branch 'origin/GT-3340_ghidorahrex_PR-1265_shrlnm_master' 2019-11-20 15:30:55 -05:00
shrlnm dd7e0e2097
fix typo in token finstr16 
wrong bit range definition
 2019-11-20 09:36:02 +03:00
ghidra1 1b1240a41b GT-3328 corrected sleighArgs.txt use with module dependency paths 2019-11-19 15:11:30 -05:00
Ryan Kurtz 125a3fad7d Merge remote-tracking branch 'origin/caheckman_sleighx86vector' 2019-11-19 12:33:35 -05:00
caheckman 53e4a67fa2 Bug fix in ADDPS 2019-11-19 11:38:53 -05:00
shrlnm d69dbe5c97
fix movi20 and movi20s 2019-11-19 11:43:58 +03:00
caheckman 57c081eeda psllq, psubq 2019-11-16 12:53:05 -05:00
caheckman a1623af6a0 pmulw, pslld, psubd 2019-11-16 12:36:36 -05:00
caheckman 965afc8829 Replace specialized AVX constructors with bitrange operator 2019-11-16 11:47:25 -05:00
caheckman 64d15b3ea0 Use bitrange operator instead of special constructors when accessing 
vector register lanes
 2019-11-16 10:28:09 -05:00
adamopolous 2de421d3f9 added gradle dependencies for jacoco tasks 2019-11-15 09:54:34 -05:00
Ryan Kurtz 26ce101d36 Merge remote-tracking branch 'origin/GT-3251_ghidorahrex_PR-1161_mumbel_superh_simm' 2019-11-13 08:44:40 -05:00
Ryan Kurtz 55dfda10ba Merge remote-tracking branch 'origin/patch' 2019-11-13 08:37:23 -05:00
ghidorahrex 074e3ca869 GT-3268: XGATE removed extraneous left-shift in LDH 2019-11-13 08:27:14 -05:00
ghidorahrex 0c7cf09646 GT-3306: Corrected MCS-96 xml (fixes #1224) 2019-11-13 08:20:00 -05:00
ghidorahrex b514a2c9ec GT-3254: PPC VLE Corrected signed immediate offset calculation (fixes 
#1160)
 2019-11-13 08:13:19 -05:00
ghidorahrex 2ab04ae86d GT-3256: x86 corrected disassembly of x87 escape opcodes 2019-11-13 08:07:37 -05:00
Wolfgang Schwotzer c41bdcc5cf Support Motorola M6809 2019-11-07 22:02:22 +01:00
Ryan Kurtz 7d094243d0 Merge remote-tracking branch 'origin/patch' 2019-11-06 13:32:50 -05:00
Ryan Kurtz ec079f7844 Merge remote-tracking branch 'origin/GT-3202_ghidorahrex_sparcv9_floating_point' into patch 2019-11-06 13:05:45 -05:00
Ryan Kurtz fa48768e77 GT-3106: Fixing avr8.opinion XML parse error 2019-11-05 12:27:40 -05:00
Ryan Kurtz 6bcf4cfa5f Merge remote-tracking branch 'origin/patch' 2019-11-05 11:36:35 -05:00
Ryan Kurtz c835f335fa Merge remote-tracking branch 
'origin/GT-3228_ghidorahrex_PowerPC_VLE_e_cmpi_decompilation' into patch
(fixes #1127)
 2019-11-05 10:34:29 -05:00
Ryan Kurtz 0a56eae9f6 Merge remote-tracking branch 'origin/GT-3106_ghidorahrex_AVR8_pcodetests' 2019-11-01 10:03:33 -04:00
Ryan Kurtz 14f7c1f33b Merge remote-tracking branch 'origin/patch' 2019-11-01 09:53:47 -04:00
ghidorahrex 6b81682551 GT-3253: Corrected register definitions for the x86 rdrand instruction 
(fixes #1169).
 2019-11-01 09:50:52 -04:00
Ryan Kurtz b12ebf9b60 Merge remote-tracking branch 
'origin/GT-3232_ghidorahrex_PowerPC_VLE_bit_generation' into patch
(fixes #967)
 2019-11-01 09:44:45 -04:00
ghidorahrex 8f526ee693 GT-3228: Removed unneeded temporary variables and token field. 2019-10-31 13:05:52 -04:00
caheckman 688264f999 removed unused label 2019-10-24 13:34:02 -04:00
Toshi Piazza 1a007daaba
Adds rex.W prefix encoding of J^cc on x86 
Previously ghidra could not parse the following bytes: 48 0f 85 05 00 00 00 (jne 0xc); note the 48 rex.W prefix which appears to be a no-op.
 2019-10-20 12:46:24 -07:00
mumbel cab68a3ece SuperH 2A - fix sign in action 2019-10-19 21:13:05 -05:00
Ryan Kurtz e3b8a782ba Merge remote-tracking branch 'origin/GT-3239_ryanmkurtz_PR-916_redfast00_privilaged_typo_fix' 2019-10-16 08:28:39 -04:00
ghidorahrex f871320726 GT-3202: Code review fixes, implemented data organization section 2019-10-15 13:52:31 -04:00
Ryan Kurtz 8a35b56666 Merge remote-tracking branch 'origin/GT-3230_PowerPC_bmaski' into 
Ghidra_9.1 (fixes #1123)
 2019-10-15 11:16:08 -04:00
Ryan Kurtz 3a33a8d9f3 Merge remote-tracking branch 'origin/GT-3201_SparcStackBias' into Ghidra_9.1 2019-10-15 11:05:15 -04:00
ghidorahrex dba454d348 GT-3232: Corrected PowerPC VLE bit generation for several instructions 2019-10-10 10:05:55 -04:00
ghidorahrex a3bf5f4b1c GT-3106: Corrected AVR8 variant naming mismatch. 2019-10-10 09:06:14 -04:00
ghidorahrex 3236686436 GT-3228: Corrected crall implementation for PowerPC comparisons 2019-10-09 13:39:24 -04:00
caheckman 5e41bf2df4 fix for se_bmaski, parameter first use with subtractWrap 2019-10-09 13:20:00 -04:00