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Merge remote-tracking branch 'origin/GP-58_caheckman_RiscvDecodeStates'
This commit is contained in:
ghidra1
commit
4ecf402341
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@ -6,7 +6,7 @@
|
|||
endian="little"
|
||||
size="64"
|
||||
variant="RV64I"
|
||||
version="1.0"
|
||||
version="1.1"
|
||||
slafile="riscv.lp64.sla"
|
||||
processorspec="RV64I.pspec"
|
||||
id="RISCV:LE:64:RV64I">
|
||||
|
|
@ -18,7 +18,7 @@
|
|||
endian="little"
|
||||
size="64"
|
||||
variant="RV64IC"
|
||||
version="1.0"
|
||||
version="1.1"
|
||||
slafile="riscv.lp64.sla"
|
||||
processorspec="RV64IC.pspec"
|
||||
id="RISCV:LE:64:RV64IC">
|
||||
|
|
@ -30,7 +30,7 @@
|
|||
endian="little"
|
||||
size="64"
|
||||
variant="RV64G"
|
||||
version="1.0"
|
||||
version="1.1"
|
||||
slafile="riscv.lp64d.sla"
|
||||
processorspec="RV64G.pspec"
|
||||
id="RISCV:LE:64:RV64G">
|
||||
|
|
@ -42,7 +42,7 @@
|
|||
endian="little"
|
||||
size="64"
|
||||
variant="RV64GC"
|
||||
version="1.0"
|
||||
version="1.1"
|
||||
slafile="riscv.lp64d.sla"
|
||||
processorspec="RV64GC.pspec"
|
||||
id="RISCV:LE:64:RV64GC">
|
||||
|
|
@ -54,7 +54,7 @@
|
|||
endian="little"
|
||||
size="64"
|
||||
variant="default"
|
||||
version="1.0"
|
||||
version="1.1"
|
||||
slafile="riscv.lp64d.sla"
|
||||
processorspec="RV64GC.pspec"
|
||||
id="RISCV:LE:64:default">
|
||||
|
|
@ -66,7 +66,7 @@
|
|||
endian="little"
|
||||
size="32"
|
||||
variant="RV32I"
|
||||
version="1.0"
|
||||
version="1.1"
|
||||
slafile="riscv.ilp32.sla"
|
||||
processorspec="RV32I.pspec"
|
||||
id="RISCV:LE:32:RV32I">
|
||||
|
|
@ -78,7 +78,7 @@
|
|||
endian="little"
|
||||
size="32"
|
||||
variant="RV32IC"
|
||||
version="1.0"
|
||||
version="1.1"
|
||||
slafile="riscv.ilp32.sla"
|
||||
processorspec="RV32IC.pspec"
|
||||
id="RISCV:LE:32:RV32IC">
|
||||
|
|
@ -90,7 +90,7 @@
|
|||
endian="little"
|
||||
size="32"
|
||||
variant="RV32IMC"
|
||||
version="1.0"
|
||||
version="1.1"
|
||||
slafile="riscv.ilp32.sla"
|
||||
processorspec="RV32IMC.pspec"
|
||||
id="RISCV:LE:32:RV32IMC">
|
||||
|
|
@ -102,7 +102,7 @@
|
|||
endian="little"
|
||||
size="32"
|
||||
variant="RV32G"
|
||||
version="1.0"
|
||||
version="1.1"
|
||||
slafile="riscv.ilp32d.sla"
|
||||
processorspec="RV32G.pspec"
|
||||
id="RISCV:LE:32:RV32G">
|
||||
|
|
@ -114,7 +114,7 @@
|
|||
endian="little"
|
||||
size="32"
|
||||
variant="RV32GC"
|
||||
version="1.0"
|
||||
version="1.1"
|
||||
slafile="riscv.ilp32d.sla"
|
||||
processorspec="RV32GC.pspec"
|
||||
id="RISCV:LE:32:RV32GC">
|
||||
|
|
@ -126,7 +126,7 @@
|
|||
endian="little"
|
||||
size="32"
|
||||
variant="default"
|
||||
version="1.0"
|
||||
version="1.1"
|
||||
slafile="riscv.ilp32d.sla"
|
||||
processorspec="RV32GC.pspec"
|
||||
id="RISCV:LE:32:default">
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
|
||||
|
||||
# fadd.d D,S,T,m 02000053 fe00007f SIMPLE (0, 0)
|
||||
:fadd.d frd,frs1D,frs2D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x1
|
||||
:fadd.d frd,frs1D,frs2D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x1
|
||||
{
|
||||
frd = frs1D f+ frs2D;
|
||||
}
|
||||
|
|
@ -69,7 +69,7 @@
|
|||
|
||||
|
||||
# fcvt.s.d D,S,m 40100053 fff0007f SIMPLE (0, 0)
|
||||
:fcvt.s.d frd,frs1D,FRM is RV32 & RVD & frs1D & frd & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x20 & op2024=0x1
|
||||
:fcvt.s.d frd,frs1D,FRM is RV32 & RVD & frs1D & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x20 & op2024=0x1
|
||||
{
|
||||
local tmp:4 = float2float(frs1D);
|
||||
frd = zext(tmp);
|
||||
|
|
@ -84,7 +84,7 @@
|
|||
|
||||
|
||||
# fcvt.w.d d,S,m c2000053 fff0007f SIMPLE (0, 0)
|
||||
:fcvt.w.d rdW,frs1D,FRM is RV32 & RVD & frs1D & FRM & op1214!=7 & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x0
|
||||
:fcvt.w.d rdW,frs1D,FRM is RV32 & RVD & frs1D & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x0
|
||||
{
|
||||
rdW = trunc(frs1D);
|
||||
}
|
||||
|
|
@ -99,7 +99,7 @@
|
|||
|
||||
|
||||
# fcvt.wu.d d,S,m c2100053 fff0007f SIMPLE (0, 0)
|
||||
:fcvt.wu.d rdW,frs1D,FRM is RV32 & RVD & frs1D & FRM & op1214!=7 & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x1
|
||||
:fcvt.wu.d rdW,frs1D,FRM is RV32 & RVD & frs1D & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x1
|
||||
{
|
||||
#TODO unsigned
|
||||
rdW = trunc(frs1D);
|
||||
|
|
@ -114,7 +114,7 @@
|
|||
|
||||
|
||||
# fdiv.d D,S,T,m 1a000053 fe00007f SIMPLE (0, 0)
|
||||
:fdiv.d frd,frs1D,frs2D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xd
|
||||
:fdiv.d frd,frs1D,frs2D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xd
|
||||
{
|
||||
frd = frs1D f/ frs2D;
|
||||
}
|
||||
|
|
@ -158,7 +158,7 @@
|
|||
|
||||
|
||||
# fmadd.d D,S,T,R,m 02000043 0600007f SIMPLE (0, 0)
|
||||
:fmadd.d frd,frs1D,frs2D,frs3D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op1214!=7 & frs3D & op0001=0x3 & op0204=0x0 & op0506=0x2 & op2526=0x1
|
||||
:fmadd.d frd,frs1D,frs2D,frs3D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & frs3D & op0001=0x3 & op0204=0x0 & op0506=0x2 & op2526=0x1
|
||||
{
|
||||
frd = (frs1D f* frs2D) f+ frs3D;
|
||||
}
|
||||
|
|
@ -204,7 +204,7 @@
|
|||
|
||||
|
||||
# fmsub.d D,S,T,R,m 02000047 0600007f SIMPLE (0, 0)
|
||||
:fmsub.d frd,frs1D,frs2D,frs3D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op1214!=7 & frs3D & op0001=0x3 & op0204=0x1 & op0506=0x2 & op2526=0x1
|
||||
:fmsub.d frd,frs1D,frs2D,frs3D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & frs3D & op0001=0x3 & op0204=0x1 & op0506=0x2 & op2526=0x1
|
||||
{
|
||||
frd = (frs1D f* frs2D) f- frs3D;
|
||||
}
|
||||
|
|
@ -218,7 +218,7 @@
|
|||
|
||||
|
||||
# fmul.d D,S,T,m 12000053 fe00007f SIMPLE (0, 0)
|
||||
:fmul.d frd,frs1D,frs2D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x9
|
||||
:fmul.d frd,frs1D,frs2D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x9
|
||||
{
|
||||
frd = frs1D f* frs2D;
|
||||
}
|
||||
|
|
@ -232,7 +232,7 @@
|
|||
|
||||
|
||||
# fnmadd.d D,S,T,R,m 0200004f 0600007f SIMPLE (0, 0)
|
||||
:fnmadd.d frd,frs1D,frs2D,frs3D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op1214!=7 & frs3D & op0001=0x3 & op0204=0x3 & op0506=0x2 & op2526=0x1
|
||||
:fnmadd.d frd,frs1D,frs2D,frs3D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & frs3D & op0001=0x3 & op0204=0x3 & op0506=0x2 & op2526=0x1
|
||||
{
|
||||
frd = (f- (frs1D f* frs2D)) f- frs3D;
|
||||
}
|
||||
|
|
@ -246,7 +246,7 @@
|
|||
|
||||
|
||||
# fnmsub.d D,S,T,R,m 0200004b 0600007f SIMPLE (0, 0)
|
||||
:fnmsub.d frd,frs1D,frs2D,frs3D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op1214!=7 & frs3D & op0001=0x3 & op0204=0x2 & op0506=0x2 & op2526=0x1
|
||||
:fnmsub.d frd,frs1D,frs2D,frs3D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & frs3D & op0001=0x3 & op0204=0x2 & op0506=0x2 & op2526=0x1
|
||||
{
|
||||
frd = (f- (frs1D f* frs2D)) f+ frs3D;
|
||||
}
|
||||
|
|
@ -261,7 +261,7 @@
|
|||
|
||||
|
||||
# fsgnj.d D,S,T 22000053 fe00707f SIMPLE (0, 0)
|
||||
:fsgnj.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x11 & op1519!=op2024
|
||||
:fsgnj.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x11
|
||||
{
|
||||
local tmp:$(DFLEN) = frs1D;
|
||||
tmp[63,1] = frs2D[63,1];
|
||||
|
|
@ -276,7 +276,7 @@
|
|||
|
||||
|
||||
# fsgnjn.d D,S,T 22001053 fe00707f SIMPLE (0, 0)
|
||||
:fsgnjn.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x11 & op1519!=op2024
|
||||
:fsgnjn.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x11
|
||||
{
|
||||
local tmp:$(DFLEN) = frs1D;
|
||||
tmp[63,1] = !frs2D[63,1];
|
||||
|
|
@ -291,7 +291,7 @@
|
|||
|
||||
|
||||
# fsgnjx.d D,S,T 22002053 fe00707f SIMPLE (0, 0)
|
||||
:fsgnjx.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x11 & op1519!=op2024
|
||||
:fsgnjx.d frd,frs1D,frs2D is RV32 & RVD & frs1D & frd & frs2D & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x11
|
||||
{
|
||||
local tmp:$(DFLEN) = frs1D;
|
||||
tmp[63,1] = tmp[63,1] ^ frs2D[63,1];
|
||||
|
|
@ -313,7 +313,7 @@
|
|||
|
||||
|
||||
# fsqrt.d D,S,m 5a000053 fff0007f SIMPLE (0, 0)
|
||||
:fsqrt.d frd,frs1D,FRM is RV32 & RVD & frs1D & frd & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x2d & op2024=0x0
|
||||
:fsqrt.d frd,frs1D,FRM is RV32 & RVD & frs1D & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x2d & op2024=0x0
|
||||
{
|
||||
frd = sqrt(frs1D);
|
||||
}
|
||||
|
|
@ -327,7 +327,7 @@
|
|||
|
||||
|
||||
# fsub.d D,S,T,m 0a000053 fe00007f SIMPLE (0, 0)
|
||||
:fsub.d frd,frs1D,frs2D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x5
|
||||
:fsub.d frd,frs1D,frs2D,FRM is RV32 & RVD & frs1D & frd & frs2D & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x5
|
||||
{
|
||||
frd = frs1D f- frs2D;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
|
||||
|
||||
# fadd.s D,S,T,m 00000053 fe00007f SIMPLE (0, 0)
|
||||
:fadd.s frd,frs1S,frs2S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x0
|
||||
:fadd.s frd,frs1S,frs2S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x0
|
||||
{
|
||||
local tmp:4 = frs1S f+ frs2S;
|
||||
fassignS(frd, tmp);
|
||||
|
|
@ -45,7 +45,7 @@
|
|||
|
||||
|
||||
# fcvt.s.w D,s,m d0000053 fff0007f SIMPLE (0, 0)
|
||||
:fcvt.s.w frd,rs1W,FRM is RV32 & RVF & frd & FRM & op1214!=7 & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x0
|
||||
:fcvt.s.w frd,rs1W,FRM is RV32 & RVF & frd & FRM & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x0
|
||||
{
|
||||
local tmp:4 = int2float(rs1W);
|
||||
fassignS(frd, tmp);
|
||||
|
|
@ -63,7 +63,7 @@
|
|||
|
||||
|
||||
# fcvt.s.wu D,s,m d0100053 fff0007f SIMPLE (0, 0)
|
||||
:fcvt.s.wu frd,rs1W,FRM is RV32 & RVF & frd & FRM & op1214!=7 & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x1
|
||||
:fcvt.s.wu frd,rs1W,FRM is RV32 & RVF & frd & FRM & rs1W & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x1
|
||||
{
|
||||
#ATTN unsigned can be an issue here
|
||||
local u32:$(XLEN2) = zext(rs1W);
|
||||
|
|
@ -79,7 +79,7 @@
|
|||
}
|
||||
|
||||
# fcvt.w.s d,S,m c0000053 fff0007f SIMPLE (0, 0)
|
||||
:fcvt.w.s rdW,frs1S,FRM is RV32 & RVF & frs1S & FRM & op1214!=7 & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x0
|
||||
:fcvt.w.s rdW,frs1S,FRM is RV32 & RVF & frs1S & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x0
|
||||
{
|
||||
rdW = trunc(frs1S);
|
||||
}
|
||||
|
|
@ -93,7 +93,7 @@
|
|||
}
|
||||
|
||||
# fcvt.wu.s d,S,m c0100053 fff0007f SIMPLE (0, 0)
|
||||
:fcvt.wu.s rdW,frs1S,FRM is RV32 & RVF & frs1S & FRM & op1214!=7 & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x1
|
||||
:fcvt.wu.s rdW,frs1S,FRM is RV32 & RVF & frs1S & FRM & rdW & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x1
|
||||
{
|
||||
#TODO unsigned
|
||||
rdW = trunc(frs1S);
|
||||
|
|
@ -109,7 +109,7 @@
|
|||
|
||||
|
||||
# fdiv.s D,S,T,m 18000053 fe00007f SIMPLE (0, 0)
|
||||
:fdiv.s frd,frs1S,frs2S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xc
|
||||
:fdiv.s frd,frs1S,frs2S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xc
|
||||
{
|
||||
local tmp:4 = frs1S f/ frs2S;
|
||||
fassignS(frd, tmp);
|
||||
|
|
@ -154,7 +154,7 @@
|
|||
|
||||
|
||||
# fmadd.s D,S,T,R,m 00000043 0600007f SIMPLE (0, 0)
|
||||
:fmadd.s frd,frs1S,frs2S,frs3S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op1214!=7 & frs3S & op0001=0x3 & op0204=0x0 & op0506=0x2 & op2526=0x0
|
||||
:fmadd.s frd,frs1S,frs2S,frs3S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & frs3S & op0001=0x3 & op0204=0x0 & op0506=0x2 & op2526=0x0
|
||||
{
|
||||
local tmp:4 = (frs1S f* frs2S) f+ frs3S;
|
||||
fassignS(frd, tmp);
|
||||
|
|
@ -202,7 +202,7 @@
|
|||
|
||||
|
||||
# fmsub.s D,S,T,R,m 00000047 0600007f SIMPLE (0, 0)
|
||||
:fmsub.s frd,frs1S,frs2S,frs3S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op1214!=7 & frs3S & op0001=0x3 & op0204=0x1 & op0506=0x2 & op2526=0x0
|
||||
:fmsub.s frd,frs1S,frs2S,frs3S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & frs3S & op0001=0x3 & op0204=0x1 & op0506=0x2 & op2526=0x0
|
||||
{
|
||||
local tmp:4 = (frs1S f* frs2S) f- frs3S;
|
||||
fassignS(frd, tmp);
|
||||
|
|
@ -217,7 +217,7 @@
|
|||
}
|
||||
|
||||
# fmul.s D,S,T,m 10000053 fe00007f SIMPLE (0, 0)
|
||||
:fmul.s frd,frs1S,frs2S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x8
|
||||
:fmul.s frd,frs1S,frs2S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x8
|
||||
{
|
||||
local tmp:4 = frs1S f* frs2S;
|
||||
fassignS(frd, tmp);
|
||||
|
|
@ -246,7 +246,7 @@
|
|||
|
||||
|
||||
# fnmadd.s D,S,T,R,m 0000004f 0600007f SIMPLE (0, 0)
|
||||
:fnmadd.s frd,frs1S,frs2S,frs3S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op1214!=7 & frs3S & op0001=0x3 & op0204=0x3 & op0506=0x2 & op2526=0x0
|
||||
:fnmadd.s frd,frs1S,frs2S,frs3S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & frs3S & op0001=0x3 & op0204=0x3 & op0506=0x2 & op2526=0x0
|
||||
{
|
||||
local tmp:4 = (f- (frs1S f* frs2S)) f- frs3S;
|
||||
fassignS(frd, tmp);
|
||||
|
|
@ -262,7 +262,7 @@
|
|||
|
||||
|
||||
# fnmsub.s D,S,T,R,m 0000004b 0600007f SIMPLE (0, 0)
|
||||
:fnmsub.s frd,frs1S,frs2S,frs3S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op1214!=7 & frs3S & op0001=0x3 & op0204=0x2 & op0506=0x2 & op2526=0x0
|
||||
:fnmsub.s frd,frs1S,frs2S,frs3S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & frs3S & op0001=0x3 & op0204=0x2 & op0506=0x2 & op2526=0x0
|
||||
{
|
||||
local tmp:4 = (f- (frs1S f* frs2S)) f+ frs3S;
|
||||
fassignS(frd, tmp);
|
||||
|
|
@ -270,7 +270,7 @@
|
|||
|
||||
|
||||
# fsgnj.s D,S,T 20000053 fe00707f SIMPLE (0, 0)
|
||||
:fsgnj.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x10 & op1519!=op2024
|
||||
:fsgnj.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x0 & funct7=0x10
|
||||
{
|
||||
local tmp:$(SFLEN) = frs1S;
|
||||
tmp[31,1] = frs2S[31,1];
|
||||
|
|
@ -285,7 +285,7 @@
|
|||
|
||||
|
||||
# fsgnjn.s D,S,T 20001053 fe00707f SIMPLE (0, 0)
|
||||
:fsgnjn.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x10 & op1519!=op2024
|
||||
:fsgnjn.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x1 & funct7=0x10
|
||||
{
|
||||
local tmp:$(SFLEN) = frs1S;
|
||||
tmp[31,1] = !frs2S[31,1];
|
||||
|
|
@ -301,7 +301,7 @@
|
|||
|
||||
|
||||
# fsgnjx.s D,S,T 20002053 fe00707f SIMPLE (0, 0)
|
||||
:fsgnjx.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x10 & op1519!=op2024
|
||||
:fsgnjx.s frd,frs1S,frs2S is RV32 & RVF & frs1S & frd & frs2S & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct3=0x2 & funct7=0x10
|
||||
{
|
||||
local tmp:$(SFLEN) = frs1S;
|
||||
tmp[31,1] = tmp[31,1] ^ frs2S[31,1];
|
||||
|
|
@ -325,7 +325,7 @@
|
|||
|
||||
|
||||
# fsqrt.s D,S,m 58000053 fff0007f SIMPLE (0, 0)
|
||||
:fsqrt.s frd,frs1S,FRM is RV32 & RVF & frs1S & frd & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x2c & op2024=0x0
|
||||
:fsqrt.s frd,frs1S,FRM is RV32 & RVF & frs1S & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x2c & op2024=0x0
|
||||
{
|
||||
local tmp:4 = sqrt(frs1S);
|
||||
fassignS(frd, tmp);
|
||||
|
|
@ -341,7 +341,7 @@
|
|||
|
||||
|
||||
# fsub.s D,S,T,m 08000053 fe00007f SIMPLE (0, 0)
|
||||
:fsub.s frd,frs1S,frs2S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x4
|
||||
:fsub.s frd,frs1S,frs2S,FRM is RV32 & RVF & frs1S & frd & frs2S & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x4
|
||||
{
|
||||
local tmp:4 = frs1S f- frs2S;
|
||||
fassignS(frd, tmp);
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
|
||||
|
||||
# addi d,s,j 00000013 0000707f SIMPLE (0, 0)
|
||||
:addi rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op2031!=0 & op1519!=0
|
||||
:addi rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0
|
||||
{
|
||||
rd = rs1 + immI;
|
||||
}
|
||||
|
|
@ -28,15 +28,18 @@
|
|||
}
|
||||
|
||||
# li d,j 00000013 000ff07f ALIAS (0, 0)
|
||||
:li rd,immI is RV32 & RVI & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op1519=0x0 & op2031!=0
|
||||
:li rd,immI is RV32 & RVI & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op1519=0x0
|
||||
{
|
||||
#TODO alias of addi rd,zero,0x0 is an issue
|
||||
# choosing between: mv rd,zero and li rd,0x0
|
||||
#ATTN this implementation uses mv rd,zero
|
||||
rd = immI;
|
||||
}
|
||||
|
||||
|
||||
# Resolve conflict between: mv rd,zero and li rd,0x0
|
||||
# ATTN this implementation uses mv rd,zero
|
||||
:mv rd,rs1 is RV32 & RVI & rs1 & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x0 & op1531=0x0
|
||||
{
|
||||
rd = rs1;
|
||||
}
|
||||
|
||||
# and d,s,t 00007033 fe00707f SIMPLE (0, 0)
|
||||
:and rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x7 & funct7=0x0
|
||||
|
|
@ -119,7 +122,7 @@
|
|||
}
|
||||
|
||||
# jal d,a 0000006f 0000007f JSR (0, 0)
|
||||
:jal rd,immUJ is RV32 & RVI & immUJ & rd & op0711!=0 & op0001=0x3 & op0204=0x3 & op0506=0x3
|
||||
:jal rd,immUJ is RV32 & RVI & immUJ & rd & op0001=0x3 & op0204=0x3 & op0506=0x3
|
||||
{
|
||||
rd = inst_next;
|
||||
call immUJ;
|
||||
|
|
@ -133,7 +136,7 @@
|
|||
|
||||
|
||||
# jalr d,s,j 00000067 0000707f JSR (0, 0)
|
||||
:jalr rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711!=0
|
||||
:jalr rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0
|
||||
{
|
||||
local ea:$(XLEN) = (rs1 + immI) & ~1;
|
||||
rd = inst_next;
|
||||
|
|
@ -141,14 +144,14 @@
|
|||
}
|
||||
|
||||
# jr o(s) 00000067 00007fff BRANCH|ALIAS (0, 0)
|
||||
:jr immI(rs1) is RV32 & RVI & immI & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031!=0
|
||||
:jr immI(rs1) is RV32 & RVI & immI & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0
|
||||
{
|
||||
local ea:$(XLEN) = (rs1 + immI) & ~1;
|
||||
goto [ea];
|
||||
}
|
||||
|
||||
# jr s 00000067 fff07fff BRANCH|ALIAS (0, 0)
|
||||
:jr rs1 is RV32 & RVI & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031=0x0 & op1519>1
|
||||
:jr rs1 is RV32 & RVI & rs1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 & op0711=0x0 & op2031=0x0
|
||||
{
|
||||
local ea:$(XLEN) = rs1 & ~1;
|
||||
goto [ea];
|
||||
|
|
@ -313,7 +316,7 @@
|
|||
|
||||
|
||||
# sub d,s,t 40000033 fe00707f SIMPLE (0, 0)
|
||||
:sub rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x20 & op1519!=0
|
||||
:sub rd,rs1,rs2 is RV32 & RVI & rs1 & rs2 & rd & op0001=0x3 & op0204=0x4 & op0506=0x1 & funct3=0x0 & funct7=0x20
|
||||
{
|
||||
rd = rs1 - rs2;
|
||||
}
|
||||
|
|
@ -347,7 +350,7 @@
|
|||
|
||||
|
||||
# xori d,s,j 00004013 0000707f SIMPLE (0, 0)
|
||||
:xori rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x4 & op2031!=0xfff
|
||||
:xori rd,rs1,immI is RV32 & RVI & rs1 & immI & rd & op0001=0x3 & op0204=0x4 & op0506=0x0 & funct3=0x4
|
||||
{
|
||||
rd = rs1 ^ immI;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
}
|
||||
|
||||
# fadd.q D,S,T,m 06000053 fe00007f SIMPLE (0, 0)
|
||||
:fadd.q frd,frs1,frs2,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x3
|
||||
:fadd.q frd,frs1,frs2,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x3
|
||||
{
|
||||
frd = frs1 f+ frs2;
|
||||
}
|
||||
|
|
@ -42,7 +42,7 @@
|
|||
}
|
||||
|
||||
# fcvt.d.q D,S,m 42300053 fff0007f SIMPLE (0, 0)
|
||||
:fcvt.d.q frd,frs1,FRM is RV32 & RVQ & frs1 & frd & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x21 & op2024=0x3
|
||||
:fcvt.d.q frd,frs1,FRM is RV32 & RVQ & frs1 & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x21 & op2024=0x3
|
||||
{
|
||||
#TODO double to quad
|
||||
}
|
||||
|
|
@ -78,7 +78,7 @@
|
|||
}
|
||||
|
||||
# fcvt.s.q D,S,m 40300053 fff0007f SIMPLE (0, 0)
|
||||
:fcvt.s.q frd,frs1,FRM is RV32 & RVQ & frs1 & frd & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x20 & op2024=0x3
|
||||
:fcvt.s.q frd,frs1,FRM is RV32 & RVQ & frs1 & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x20 & op2024=0x3
|
||||
{
|
||||
frd = float2float(frs1);
|
||||
}
|
||||
|
|
@ -90,7 +90,7 @@
|
|||
}
|
||||
|
||||
# fcvt.w.q d,S,m c6000053 fff0007f SIMPLE (0, 0)
|
||||
:fcvt.w.q rd,frs1,FRM is RV32 & RVQ & frs1 & FRM & op1214!=7 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x0
|
||||
:fcvt.w.q rd,frs1,FRM is RV32 & RVQ & frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x0
|
||||
{
|
||||
rd = trunc(frs1);
|
||||
}
|
||||
|
|
@ -102,7 +102,7 @@
|
|||
}
|
||||
|
||||
# fcvt.wu.q d,S,m c6100053 fff0007f SIMPLE (0, 0)
|
||||
:fcvt.wu.q rd,frs1,FRM is RV32 & RVQ & frs1 & FRM & op1214!=7 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x1
|
||||
:fcvt.wu.q rd,frs1,FRM is RV32 & RVQ & frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x1
|
||||
{
|
||||
rd = trunc(frs1);
|
||||
}
|
||||
|
|
@ -119,7 +119,7 @@
|
|||
|
||||
|
||||
# fdiv.q D,S,T,m 1e000053 fe00007f SIMPLE (0, 0)
|
||||
:fdiv.q frd,frs1,frs2,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xf
|
||||
:fdiv.q frd,frs1,frs2,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xf
|
||||
{
|
||||
local tfrs1:$(QFLEN) = frs1;
|
||||
local tfrs2:$(QFLEN) = frs2;
|
||||
|
|
@ -164,7 +164,7 @@
|
|||
}
|
||||
|
||||
# fmadd.q D,S,T,R,m 06000043 0600007f SIMPLE (0, 0)
|
||||
:fmadd.q frd,frs1,frs2,frs3,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op1214!=7 & frs3 & op0001=0x3 & op0204=0x0 & op0506=0x2 & op2526=0x3
|
||||
:fmadd.q frd,frs1,frs2,frs3,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & frs3 & op0001=0x3 & op0204=0x0 & op0506=0x2 & op2526=0x3
|
||||
{
|
||||
frd = (frs1 f* frs2) f+ frs3;
|
||||
}
|
||||
|
|
@ -204,7 +204,7 @@
|
|||
}
|
||||
|
||||
# fmsub.q D,S,T,R,m 06000047 0600007f SIMPLE (0, 0)
|
||||
:fmsub.q frd,frs1,frs2,frs3,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op1214!=7 & frs3 & op0001=0x3 & op0204=0x1 & op0506=0x2 & op2526=0x3
|
||||
:fmsub.q frd,frs1,frs2,frs3,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & frs3 & op0001=0x3 & op0204=0x1 & op0506=0x2 & op2526=0x3
|
||||
{
|
||||
frd = (frs1 f* frs2) f- frs3;
|
||||
}
|
||||
|
|
@ -216,7 +216,7 @@
|
|||
}
|
||||
|
||||
# fmul.q D,S,T,m 16000053 fe00007f SIMPLE (0, 0)
|
||||
:fmul.q frd,frs1,frs2,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xb
|
||||
:fmul.q frd,frs1,frs2,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0xb
|
||||
{
|
||||
frd = frs1 f* frs2;
|
||||
}
|
||||
|
|
@ -243,7 +243,7 @@
|
|||
}
|
||||
|
||||
# fnmadd.q D,S,T,R,m 0600004f 0600007f SIMPLE (0, 0)
|
||||
:fnmadd.q frd,frs1,frs2,frs3,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op1214!=7 & frs3 & op0001=0x3 & op0204=0x3 & op0506=0x2 & op2526=0x3
|
||||
:fnmadd.q frd,frs1,frs2,frs3,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & frs3 & op0001=0x3 & op0204=0x3 & op0506=0x2 & op2526=0x3
|
||||
{
|
||||
frd = (f- (frs1 f* frs2)) f- frs3;
|
||||
}
|
||||
|
|
@ -255,7 +255,7 @@
|
|||
}
|
||||
|
||||
# fnmsub.q D,S,T,R,m 0600004b 0600007f SIMPLE (0, 0)
|
||||
:fnmsub.q frd,frs1,frs2,frs3,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op1214!=7 & frs3 & op0001=0x3 & op0204=0x2 & op0506=0x2 & op2526=0x3
|
||||
:fnmsub.q frd,frs1,frs2,frs3,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & frs3 & op0001=0x3 & op0204=0x2 & op0506=0x2 & op2526=0x3
|
||||
{
|
||||
frd = (f- (frs1 f* frs2)) f+ frs3;
|
||||
}
|
||||
|
|
@ -301,7 +301,7 @@
|
|||
}
|
||||
|
||||
# fsqrt.q D,S,m 5e000053 fff0007f SIMPLE (0, 0)
|
||||
:fsqrt.q frd,frs1,FRM is RV32 & RVQ & frs1 & frd & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x2f & op2024=0x0
|
||||
:fsqrt.q frd,frs1,FRM is RV32 & RVQ & frs1 & frd & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x2f & op2024=0x0
|
||||
{
|
||||
frd = sqrt(frs1);
|
||||
}
|
||||
|
|
@ -314,7 +314,7 @@
|
|||
}
|
||||
|
||||
# fsub.q D,S,T,m 0e000053 fe00007f SIMPLE (0, 0)
|
||||
:fsub.q frd,frs1,frs2,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op1214!=7 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x7
|
||||
:fsub.q frd,frs1,frs2,FRM is RV32 & RVQ & frs1 & frd & frs2 & FRM & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x7
|
||||
{
|
||||
frd = frs1 f- frs2;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
|
||||
|
||||
# fcvt.d.l D,s,m d2200053 fff0007f SIMPLE (64, 0)
|
||||
:fcvt.d.l frd,rs1L,FRM is RV64 & RVD & frd & FRM & op1214!=7 & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x69 & op2024=0x2
|
||||
:fcvt.d.l frd,rs1L,FRM is RV64 & RVD & frd & FRM & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x69 & op2024=0x2
|
||||
{
|
||||
local tmp:8 = int2float(rs1L);
|
||||
frd = tmp;
|
||||
|
|
@ -29,7 +29,7 @@
|
|||
|
||||
|
||||
# fcvt.d.lu D,s,m d2300053 fff0007f SIMPLE (64, 0)
|
||||
:fcvt.d.lu frd,rs1L,FRM is RV64 & RVD & frd & FRM & op1214!=7 & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x69 & op2024=0x3
|
||||
:fcvt.d.lu frd,rs1L,FRM is RV64 & RVD & frd & FRM & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x69 & op2024=0x3
|
||||
{
|
||||
#ATTN unsigned can be an issue here
|
||||
local u64:$(XLEN2) = zext(rs1L);
|
||||
|
|
@ -46,7 +46,7 @@
|
|||
|
||||
|
||||
# fcvt.l.d d,S,m c2200053 fff0007f SIMPLE (64, 0)
|
||||
:fcvt.l.d rdL,frs1D,FRM is RV64 & RVD & frs1D & FRM & op1214!=7 & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x2
|
||||
:fcvt.l.d rdL,frs1D,FRM is RV64 & RVD & frs1D & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x2
|
||||
{
|
||||
rdL = trunc(frs1D);
|
||||
}
|
||||
|
|
@ -61,7 +61,7 @@
|
|||
|
||||
|
||||
# fcvt.lu.d d,S,m c2300053 fff0007f SIMPLE (64, 0)
|
||||
:fcvt.lu.d rdL,frs1D,FRM is RV64 & RVD & frs1D & FRM & op1214!=7 & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x3
|
||||
:fcvt.lu.d rdL,frs1D,FRM is RV64 & RVD & frs1D & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x61 & op2024=0x3
|
||||
{
|
||||
#TODO unsigned
|
||||
rdL = trunc(frs1D);
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
|
||||
|
||||
# fcvt.l.s d,S,m c0200053 fff0007f SIMPLE (64, 0)
|
||||
:fcvt.l.s rdL,frs1S,FRM is RV64 & RVF & frs1S & FRM & op1214!=7 & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x2
|
||||
:fcvt.l.s rdL,frs1S,FRM is RV64 & RVF & frs1S & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x2
|
||||
{
|
||||
rdL = trunc(frs1S);
|
||||
}
|
||||
|
|
@ -25,7 +25,7 @@
|
|||
|
||||
|
||||
# fcvt.lu.s d,S,m c0300053 fff0007f SIMPLE (64, 0)
|
||||
:fcvt.lu.s rdL,frs1S,FRM is RV64 & RVF & frs1S & FRM & op1214!=7 & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x3
|
||||
:fcvt.lu.s rdL,frs1S,FRM is RV64 & RVF & frs1S & FRM & rdL & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x60 & op2024=0x3
|
||||
{
|
||||
#TODO unsigned
|
||||
rdL = trunc(frs1S);
|
||||
|
|
@ -41,7 +41,7 @@
|
|||
|
||||
|
||||
# fcvt.s.l D,s,m d0200053 fff0007f SIMPLE (64, 0)
|
||||
:fcvt.s.l frd,rs1L,FRM is RV64 & RVF & frd & FRM & op1214!=7 & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x2
|
||||
:fcvt.s.l frd,rs1L,FRM is RV64 & RVF & frd & FRM & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x2
|
||||
{
|
||||
local tmp:4 = int2float(rs1L);
|
||||
fassignS(frd, tmp);
|
||||
|
|
@ -59,7 +59,7 @@
|
|||
|
||||
|
||||
# fcvt.s.lu D,s,m d0300053 fff0007f SIMPLE (64, 0)
|
||||
:fcvt.s.lu frd,rs1L,FRM is RV64 & RVF & frd & FRM & op1214!=7 & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x3
|
||||
:fcvt.s.lu frd,rs1L,FRM is RV64 & RVF & frd & FRM & rs1L & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x68 & op2024=0x3
|
||||
{
|
||||
#ATTN unsigned can be an issue here
|
||||
local u64:$(XLEN2) = zext(rs1L);
|
||||
|
|
|
|||
|
|
@ -108,7 +108,7 @@
|
|||
|
||||
|
||||
# subw d,s,t 4000003b fe00707f SIMPLE (64, 0)
|
||||
:subw rd,rs1W,rs2W is RV64 & RVI & rs1W & rs2W & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x20 & op1519!=0
|
||||
:subw rd,rs1W,rs2W is RV64 & RVI & rs1W & rs2W & rd & op0001=0x3 & op0204=0x6 & op0506=0x1 & funct3=0x0 & funct7=0x20
|
||||
{
|
||||
local result = rs1W - rs2W;
|
||||
rd = sext(result);
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@
|
|||
|
||||
|
||||
# fcvt.l.q d,S,m c6200053 fff0007f SIMPLE (64, 0)
|
||||
:fcvt.l.q rd,frs1,FRM is RV64 & RVQ & frs1 & FRM & op1214!=7 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x2
|
||||
:fcvt.l.q rd,frs1,FRM is RV64 & RVQ & frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x2
|
||||
{
|
||||
rd = trunc(frs1);
|
||||
}
|
||||
|
|
@ -26,7 +26,7 @@
|
|||
|
||||
|
||||
# fcvt.lu.q d,S,m c6300053 fff0007f SIMPLE (64, 0)
|
||||
:fcvt.lu.q rd,frs1,FRM is RV64 & RVQ & frs1 & FRM & op1214!=7 & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x3
|
||||
:fcvt.lu.q rd,frs1,FRM is RV64 & RVQ & frs1 & FRM & rd & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x63 & op2024=0x3
|
||||
{
|
||||
rd = trunc(frs1);
|
||||
}
|
||||
|
|
@ -40,7 +40,7 @@
|
|||
|
||||
|
||||
# fcvt.q.l D,s,m d6200053 fff0007f SIMPLE (64, 0)
|
||||
:fcvt.q.l frd,rs1,FRM is RV64 & RVQ & frd & FRM & op1214!=7 & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x6b & op2024=0x2
|
||||
:fcvt.q.l frd,rs1,FRM is RV64 & RVQ & frd & FRM & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x6b & op2024=0x2
|
||||
{
|
||||
frd = int2float(rs1);
|
||||
}
|
||||
|
|
@ -54,7 +54,7 @@
|
|||
|
||||
|
||||
# fcvt.q.lu D,s,m d6300053 fff0007f SIMPLE (64, 0)
|
||||
:fcvt.q.lu frd,rs1,FRM is RV64 & RVQ & frd & FRM & op1214!=7 & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x6b & op2024=0x3
|
||||
:fcvt.q.lu frd,rs1,FRM is RV64 & RVQ & frd & FRM & rs1 & op0001=0x3 & op0204=0x4 & op0506=0x2 & funct7=0x6b & op2024=0x3
|
||||
{
|
||||
frd = int2float(rs1);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,14 +1,20 @@
|
|||
# RVC Standard Extension for Compressed Instructions
|
||||
|
||||
|
||||
# c.add d,CV 00009002 0000f003 SIMPLE (0, 0)
|
||||
:c.add crd,crs2 is RVC & crd & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x1 & cop0711!=0 & cop0206!=0
|
||||
# c.add d,CV 00009002 0000f003 SIMPLE (0, 0)
|
||||
:c.add crd,crs2 is RVC & crd & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x1
|
||||
{
|
||||
crd = crd + crs2;
|
||||
}
|
||||
|
||||
# c.addi d,Co 00000001 0000e003 SIMPLE (0, 0)
|
||||
:c.addi crd,cimmI is RVC & crd & cimmI & cop0001=0x1 & cop1315=0x0 & cop0711!=0 & (cop1212!=0 | cop0206!=0)
|
||||
# c.ebreak 00009002 0000ffff SIMPLE (0, 0)
|
||||
:c.ebreak is RVC & cop0001=0x2 & cop1315=0x4 & cop0212=0x400
|
||||
{
|
||||
}
|
||||
|
||||
# c.addi d,Co 00000001 0000e003 SIMPLE (0, 0)
|
||||
# There may be other nop forms here if (cop0711=0) or (cop1212=0 & cop0206=0)
|
||||
:c.addi crd,cimmI is RVC & crd & cimmI & cop0001=0x1 & cop1315=0x0
|
||||
{
|
||||
crd = crd + cimmI;
|
||||
}
|
||||
|
|
@ -20,20 +26,20 @@
|
|||
}
|
||||
|
||||
# c.addi16sp Cc,CL 00006101 0000ef83 SIMPLE (0, 0)
|
||||
:c.addi16sp sp,caddi16spimm is RVC & cop0711=0x2 & caddi16spimm & sp & cop0001=0x1 & cop1315=0x3 & cop0512!=0
|
||||
:c.addi16sp sp,caddi16spimm is RVC & cop0711=0x2 & caddi16spimm & sp & cop0001=0x1 & cop1315=0x3
|
||||
{
|
||||
sp = sp + caddi16spimm;
|
||||
}
|
||||
|
||||
# c.addi4spn Ct,Cc,CK 00000000 0000e003 SIMPLE (0, 0)
|
||||
:c.addi4spn cr0204s,sp,caddi4spnimm is RVC & caddi4spnimm & cr0204s & sp & cop0001=0x0 & cop1315=0x0 & cop0512!=0
|
||||
:c.addi4spn cr0204s,sp,caddi4spnimm is RVC & caddi4spnimm & cr0204s & sp & cop0001=0x0 & cop1315=0x0
|
||||
{
|
||||
cr0204s = sp + caddi4spnimm;
|
||||
}
|
||||
|
||||
@if ADDRSIZE == "64" || ADDRSIZE == "128"
|
||||
# c.addiw d,Co 00002001 0000e003 SIMPLE (64, 0)
|
||||
:c.addiw crd,cimmI is RVC & crd & cimmI & cop0001=0x1 & cop1315=0x1 & cop0711!=0
|
||||
:c.addiw crd,cimmI is RVC & crd & cimmI & cop0001=0x1 & cop1315=0x1
|
||||
{
|
||||
local tmp:8 = crd + cimmI;
|
||||
crd = sext(tmp:4);
|
||||
|
|
@ -73,11 +79,6 @@
|
|||
if (cr0709s != 0) goto cbimm;
|
||||
}
|
||||
|
||||
# c.ebreak 00009002 0000ffff SIMPLE (0, 0)
|
||||
:c.ebreak is RVC & cop0001=0x2 & cop1315=0x4 & cop0212=0x400
|
||||
{
|
||||
}
|
||||
|
||||
@if (ADDRSIZE == "32" || ADDRSIZE == "64") && FPSIZE == "64"
|
||||
# c.fld CD,Cl(Cs) 00002000 0000e003 QWORD|DREF (0, 8)
|
||||
:c.fld cfr0204s,cldimm(cr0709s) is RVC & RVD & cfr0204s & cr0709s & cop0001=0x0 & cop1315=0x1 & cldimm
|
||||
|
|
@ -166,14 +167,14 @@
|
|||
@endif
|
||||
|
||||
# c.jalr d 00009002 0000f07f JSR (0, 0)
|
||||
:c.jalr crd is RVC & crd & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x1 & cop0711!=0
|
||||
:c.jalr crd is RVC & crd & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x1
|
||||
{
|
||||
ra = inst_next;
|
||||
call [crd];
|
||||
}
|
||||
|
||||
# c.jr d 00008002 0000f07f BRANCH (0, 0)
|
||||
:c.jr crd is RVC & crd & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x0 & cop0711>1
|
||||
:c.jr crd is RVC & crd & cop0001=0x2 & cop1315=0x4 & cop0206=0x0 & cop1212=0x0
|
||||
{
|
||||
goto [crd];
|
||||
}
|
||||
|
|
@ -203,7 +204,7 @@
|
|||
|
||||
@if ADDRSIZE == "64" || ADDRSIZE == "128"
|
||||
# c.ldsp d,Cn(Cc) 00006002 0000e003 QWORD|DREF (64, 8)
|
||||
:c.ldsp crd,cldspimm(sp) is RVC & crd & sp & cop0001=0x2 & cop1315=0x3 & cldspimm & cop0711!=0
|
||||
:c.ldsp crd,cldspimm(sp) is RVC & crd & sp & cop0001=0x2 & cop1315=0x3 & cldspimm
|
||||
{
|
||||
local ea:$(XLEN) = cldspimm + sp;
|
||||
zassignD(crd, *[ram]:8 ea);
|
||||
|
|
@ -211,7 +212,7 @@
|
|||
@endif
|
||||
|
||||
@if ADDRSIZE == "128"
|
||||
:c.lqsp crd,clqspimm(sp) is RVC & crd & sp & cop0001=0x2 & cop1315=0x3 & clqspimm & cop0711!=0
|
||||
:c.lqsp crd,clqspimm(sp) is RVC & crd & sp & cop0001=0x2 & cop1315=0x3 & clqspimm
|
||||
{
|
||||
local ea:$(XLEN) = clqspimm + sp;
|
||||
crd = *[ram]:16 ea;
|
||||
|
|
@ -219,13 +220,13 @@
|
|||
@endif
|
||||
|
||||
# c.li d,Co 00004001 0000e003 SIMPLE (0, 0)
|
||||
:c.li crd,cimmI is RVC & crd & cimmI & cop0001=0x1 & cop1315=0x2 & cop0711!=0
|
||||
:c.li crd,cimmI is RVC & crd & cimmI & cop0001=0x1 & cop1315=0x2
|
||||
{
|
||||
crd = cimmI;
|
||||
}
|
||||
|
||||
# c.lui d,Cu 00006001 0000e003 SIMPLE (0, 0)
|
||||
:c.lui crd,cbigimm is RVC & cop0711!=0 & cop0711!=2 & crd & cbigimm & cop0001=0x1 & cop1315=0x3 & cop0711!=0 & cop0711!=2 & (cop1212!=0 | cop0206!=0)
|
||||
:c.lui crd,cbigimm is RVC & crd & cbigimm & cop0001=0x1 & cop1315=0x3
|
||||
{
|
||||
crd = cbigimm << 12;
|
||||
}
|
||||
|
|
@ -238,14 +239,14 @@
|
|||
}
|
||||
|
||||
# c.lwsp d,Cm(Cc) 00004002 0000e003 SIMPLE (0, 0)
|
||||
:c.lwsp crd,clwspimm(sp) is RVC & crd & sp & cop0001=0x2 & cop1315=0x2 & clwspimm & cop0711!=0
|
||||
:c.lwsp crd,clwspimm(sp) is RVC & crd & sp & cop0001=0x2 & cop1315=0x2 & clwspimm
|
||||
{
|
||||
local ea:$(XLEN) = clwspimm + sp;
|
||||
zassignW(crd, *[ram]:4 ea);
|
||||
}
|
||||
|
||||
# c.mv d,CV 00008002 0000f003 SIMPLE (0, 0)
|
||||
:c.mv crd,crs2 is RVC & crd & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x0 & cop0711!=0 & cop0206!=0
|
||||
:c.mv crd,crs2 is RVC & crd & crs2 & cop0001=0x2 & cop1315=0x4 & cop1212=0x0
|
||||
{
|
||||
crd = crs2;
|
||||
}
|
||||
|
|
@ -275,14 +276,14 @@
|
|||
@endif
|
||||
|
||||
# c.slli d,C> 00000002 0000e003 SIMPLE (0, 0)
|
||||
:c.slli crd,c6imm is RVC & crd & c6imm & cop0001=0x2 & cop1315=0x0 & cop0711!=0
|
||||
:c.slli crd,c6imm is RVC & crd & c6imm & cop0001=0x2 & cop1315=0x0
|
||||
{
|
||||
crd = crd << c6imm;
|
||||
}
|
||||
|
||||
#TODO hint?
|
||||
# c.slli64 d 00000002 0000f07f SIMPLE (0, 0)
|
||||
:c.slli64 crd is RVC & crd & cop0001=0x2 & cop1315=0x0 & cop0206=0x0 & cop1212=0x0 & cop0711!=0
|
||||
:c.slli64 crd is RVC & crd & cop0001=0x2 & cop1315=0x0 & cop0206=0x0 & cop1212=0x0
|
||||
{
|
||||
crd = crd << 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -16,51 +16,51 @@ define pcodeop trap;
|
|||
|
||||
|
||||
# possible tokens: r0711 r1519 r2024 r2731 cr0206 cr0711 cd0711
|
||||
rs1: r1519 is r1519 & op1519!=0 { export r1519; }
|
||||
rs1: r1519 is r1519 { export r1519; }
|
||||
rs1: zero is r1519 & zero & op1519=0 { export 0:$(XLEN); }
|
||||
|
||||
rs2: r2024 is r2024 & op2024!=0 { export r2024; }
|
||||
rs2: r2024 is r2024 { export r2024; }
|
||||
rs2: zero is r2024 & zero & op2024=0 { export 0:$(XLEN); }
|
||||
|
||||
rd: r0711 is r0711 & op0711!=0 { export r0711; }
|
||||
rd: r0711 is r0711 { export r0711; }
|
||||
rd: zero is r0711 & zero & op0711=0 { export 0:$(XLEN); }
|
||||
|
||||
@if ADDRSIZE == "32"
|
||||
|
||||
rs1W: r1519 is RV32 & r1519 & op1519!=0 { export r1519; }
|
||||
rs1W: r1519 is RV32 & r1519 { export r1519; }
|
||||
rs1W: zero is RV32 & r1519 & zero & op1519=0 { export 0:$(XLEN); }
|
||||
|
||||
rs2W: r2024 is RV32 & r2024 & op2024!=0 { export r2024; }
|
||||
rs2W: r2024 is RV32 & r2024 { export r2024; }
|
||||
rs2W: zero is RV32 & r2024 & zero & op2024=0 { export 0:$(XLEN); }
|
||||
|
||||
#TODO dest may be bad, might need an assign macro
|
||||
rdW: r0711 is RV32 & r0711 & op0711!=0 { export r0711; }
|
||||
rdW: r0711 is RV32 & r0711 { export r0711; }
|
||||
rdW: zero is RV32 & r0711 & zero & op0711=0 { export 0:$(XLEN); }
|
||||
|
||||
@else
|
||||
|
||||
rs1W: r1519 is r1519 & op1519!=0 { local tmp:4 = r1519:4; export tmp; }
|
||||
rs1W: r1519 is r1519 { local tmp:4 = r1519:4; export tmp; }
|
||||
rs1W: zero is r1519 & zero & op1519=0 { export 0:4; }
|
||||
|
||||
rs2W: r2024 is r2024 & op2024!=0 { local tmp:4 = r2024:4; export tmp; }
|
||||
rs2W: r2024 is r2024 { local tmp:4 = r2024:4; export tmp; }
|
||||
rs2W: zero is r2024 & zero & op2024=0 { export 0:4; }
|
||||
|
||||
#TODO dest may be bad, might need an assign macro
|
||||
rdW: r0711 is r0711 & op0711!=0 { export r0711; }
|
||||
rdW: r0711 is r0711 { export r0711; }
|
||||
rdW: zero is r0711 & zero & op0711=0 { export 0:8; }
|
||||
|
||||
@endif
|
||||
|
||||
#TODO does this need to be in an if/endif
|
||||
@if ADDRSIZE == "64"
|
||||
rs1L: r1519 is r1519 & op1519!=0 { local tmp:8 = r1519:8; export tmp; }
|
||||
rs1L: r1519 is r1519 { local tmp:8 = r1519:8; export tmp; }
|
||||
rs1L: zero is r1519 & zero & op1519=0 { export 0:8; }
|
||||
|
||||
rs2L: r2024 is r2024 & op2024!=0 { local tmp:8 = r2024:8; export tmp; }
|
||||
rs2L: r2024 is r2024 { local tmp:8 = r2024:8; export tmp; }
|
||||
rs2L: zero is r2024 & zero & op2024=0 { export 0:8; }
|
||||
|
||||
#TODO dest may be bad, might need an assign macro
|
||||
rdL: r0711 is r0711 & op0711!=0 { export r0711; }
|
||||
rdL: r0711 is r0711 { export r0711; }
|
||||
rdL: zero is r0711 & zero & op0711=0 { export 0:8; }
|
||||
@endif
|
||||
|
||||
|
|
@ -173,13 +173,13 @@ aqrl: ".aqrl" is op2526=3 {}
|
|||
|
||||
|
||||
|
||||
crs1: cr0711 is cr0711 & cop0711!=0 { export cr0711; }
|
||||
crs1: cr0711 is cr0711 { export cr0711; }
|
||||
crs1: zero is cr0711 & zero & cop0711=0 { export 0:$(XLEN); }
|
||||
|
||||
crd: cd0711 is cd0711 & cop0711!=0 { export cd0711; }
|
||||
crd: cd0711 is cd0711 { export cd0711; }
|
||||
crd: zero is cd0711 & zero & cop0711=0 { export 0:$(XLEN); }
|
||||
|
||||
crs2: cr0206 is cr0206 & cop0206!=0 { export cr0206; }
|
||||
crs2: cr0206 is cr0206 { export cr0206; }
|
||||
crs2: zero is cr0206 & zero & cop0206=0 { export 0:$(XLEN); }
|
||||
|
||||
@if FPSIZE != ""
|
||||
|
|
|
|||
Loading…
Reference in a new issue