Frank Chang a42bd00166 target/riscv: debug: Determine the trigger type from tdata1.type ... Current RISC-V debug assumes that only type 2 trigger is supported. To allow more types of triggers to be supported in the future (e.g. type 6 trigger, which is similar to type 2 trigger with additional functionality), we should determine the trigger type from tdata1.type. RV_MAX_TRIGGERS is also introduced in replacement of TRIGGER_TYPE2_NUM. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> [bmeng: fixed MXL_RV128 case, and moved macros to the following patch] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220909134215.1843865-2-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-09-27 11:23:57 +10:00
..
insn_trans	target/riscv: Honour -semihosting-config userspace=on and enable=on	2022-09-13 17:18:21 +01:00
arch_dump.c	target-riscv: support QMP dump-guest-memory	2021-03-04 09:43:29 -05:00
bitmanip_helper.c	target/riscv: rvk: add support for zbkx extension	2022-04-29 10:47:45 +10:00
common-semi-target.h	semihosting: Split out common-semi-target.h	2022-06-28 04:35:07 +05:30
cpu-param.h	Normalize header guard symbol definition	2022-05-11 16:50:26 +02:00
cpu.c	target/riscv: Set the CPU resetvec directly	2022-09-27 07:04:38 +10:00
cpu.h	target/riscv: debug: Determine the trigger type from tdata1.type	2022-09-27 11:23:57 +10:00
cpu_bits.h	target/riscv: Remove sideleg and sedeleg	2022-09-27 07:04:38 +10:00
cpu_helper.c	target/riscv: Honour -semihosting-config userspace=on and enable=on	2022-09-13 17:18:21 +01:00
cpu_user.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
crypto_helper.c	target/riscv: rvk: add support for zksed/zksh extension	2022-04-29 10:47:45 +10:00
csr.c	target/riscv: debug: Determine the trigger type from tdata1.type	2022-09-27 11:23:57 +10:00
debug.c	target/riscv: debug: Determine the trigger type from tdata1.type	2022-09-27 11:23:57 +10:00
debug.h	target/riscv: debug: Determine the trigger type from tdata1.type	2022-09-27 11:23:57 +10:00
fpu_helper.c	target/riscv: add support for zhinx/zhinxmin	2022-03-03 13:14:50 +10:00
gdbstub.c	target/riscv: Check the correct exception cause in vector GDB stub	2022-09-27 07:04:38 +10:00
helper.h	target/riscv: rvk: add support for zksed/zksh extension	2022-04-29 10:47:45 +10:00
insn16.decode	target/riscv: fix shifts shamt value for rv128c	2022-09-07 09:18:32 +02:00
insn32.decode	target/riscv: Add Zihintpause support	2022-09-07 09:18:33 +02:00
instmap.h	target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()	2022-09-07 09:18:32 +02:00
internals.h	target/riscv: rvv: Add mask agnostic for vv instructions	2022-09-07 09:18:32 +02:00
Kconfig	meson: Introduce target-specific Kconfig	2021-07-09 18:21:34 +02:00
kvm-stub.c	target/riscv: Support setting external interrupt by KVM	2022-01-21 15:52:56 +10:00
kvm.c	Remove qemu-common.h include from most units	2022-04-06 14:31:55 +02:00
kvm_riscv.h	target/riscv: Support setting external interrupt by KVM	2022-01-21 15:52:56 +10:00
m128_helper.c	target/riscv: support for 128-bit M extension	2022-01-08 15:46:10 +10:00
machine.c	target/riscv: debug: Determine the trigger type from tdata1.type	2022-09-27 11:23:57 +10:00
meson.build	target/riscv: Add stimecmp support	2022-09-07 09:19:15 +02:00
monitor.c	target/riscv: Fix incorrect PTE merge in walk_pte	2022-04-29 10:47:46 +10:00
op_helper.c	target/riscv: rvk: add CSR support for Zkr	2022-04-29 10:47:45 +10:00
pmp.c	target/riscv/pmp: guard against PMP ranges with a negative size	2022-07-03 10:03:20 +10:00
pmp.h	target/riscv: rvk: add CSR support for Zkr	2022-04-29 10:47:45 +10:00
pmu.c	hw/riscv: virt: Add PMU DT node to the device tree	2022-09-07 09:19:15 +02:00
pmu.h	hw/riscv: virt: Add PMU DT node to the device tree	2022-09-07 09:19:15 +02:00
sbi_ecall_interface.h	Clean up ill-advised or unusual header guards	2022-05-11 16:50:01 +02:00
time_helper.c	target/riscv: Add vstimecmp support	2022-09-07 09:19:15 +02:00
time_helper.h	target/riscv: Add stimecmp support	2022-09-07 09:19:15 +02:00
trace-events	target/riscv: Add ePMP CSR access functions	2021-05-11 20:02:06 +10:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
translate.c	target/riscv: Honour -semihosting-config userspace=on and enable=on	2022-09-13 17:18:21 +01:00
vector_helper.c	target/riscv: rvv: Add mask agnostic for vector permutation instructions	2022-09-07 09:18:33 +02:00
XVentanaCondOps.decode	target/riscv: Add XVentanaCondOps custom extension	2022-02-16 12:24:18 +10:00