qemu/target/riscv/XVentanaCondOps.decode
Philipp Tomsich 0d429bd243 target/riscv: Add XVentanaCondOps custom extension
This adds the decoder and translation for the XVentanaCondOps custom
extension (vendor-defined by Ventana Micro Systems), which is
documented at https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf

This commit then also adds a guard-function (has_XVentanaCondOps_p)
and the decoder function to the table of decoders, enabling the
support for the XVentanaCondOps extension.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220202005249.3566542-7-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-02-16 12:24:18 +10:00

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Text

#
# RISC-V translation routines for the XVentanaCondOps extension
#
# Copyright (c) 2022 Dr. Philipp Tomsich, philipp.tomsich@vrull.eu
#
# SPDX-License-Identifier: LGPL-2.1-or-later
#
# Reference: VTx-family custom instructions
# Custom ISA extensions for Ventana Micro Systems RISC-V cores
# (https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf)
# Fields
%rs2 20:5
%rs1 15:5
%rd 7:5
# Argument sets
&r rd rs1 rs2 !extern
# Formats
@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
# *** RV64 Custom-3 Extension ***
vt_maskc 0000000 ..... ..... 110 ..... 1111011 @r
vt_maskcn 0000000 ..... ..... 111 ..... 1111011 @r