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Queued target/mips patches

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Merge remote-tracking branch 'remotes/aurel/tags/pull-target-mips-20170717' into staging

Queued target/mips patches

# gpg: Signature made Mon 17 Jul 2017 15:50:27 BST
# gpg:                using RSA key 0xBA9C78061DDD8C9B
# gpg: Good signature from "Aurelien Jarno <aurelien@aurel32.net>"
# gpg:                 aka "Aurelien Jarno <aurelien@jarno.fr>"
# gpg:                 aka "Aurelien Jarno <aurel32@debian.org>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 7746 2642 A9EF 94FD 0F77  196D BA9C 7806 1DDD 8C9B

* remotes/aurel/tags/pull-target-mips-20170717:
  target/mips: optimize WSBH, DSBH and DSHD
  mips: set CP0 Debug DExcCode for SDBBP instruction

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2017-07-18 11:41:03 +01:00
commit ed6458726a
2 changed files with 14 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
target/mips/helper.c
View File

@ -627,6 +627,8 @@ void mips_cpu_do_interrupt(CPUState *cs)
goto set_DEPC;
case EXCP_DBp:
env->CP0_Debug |= 1 << CP0DB_DBp;
/* Setup DExcCode - SDBBP instruction */
env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | 9 << CP0DB_DEC;
goto set_DEPC;
case EXCP_DDBS:
env->CP0_Debug |= 1 << CP0DB_DDBS;

18
target/mips/translate.c
View File

@ -4572,12 +4572,14 @@ static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd)
case OPC_WSBH:
{
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_const_tl(0x00FF00FF);
tcg_gen_shri_tl(t1, t0, 8);
tcg_gen_andi_tl(t1, t1, 0x00FF00FF);
tcg_gen_and_tl(t1, t1, t2);
tcg_gen_and_tl(t0, t0, t2);
tcg_gen_shli_tl(t0, t0, 8);
tcg_gen_andi_tl(t0, t0, ~0x00FF00FF);
tcg_gen_or_tl(t0, t0, t1);
tcg_temp_free(t2);
tcg_temp_free(t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
}
@ -4592,27 +4594,31 @@ static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd)
case OPC_DSBH:
{
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_const_tl(0x00FF00FF00FF00FFULL);
tcg_gen_shri_tl(t1, t0, 8);
tcg_gen_andi_tl(t1, t1, 0x00FF00FF00FF00FFULL);
tcg_gen_and_tl(t1, t1, t2);
tcg_gen_and_tl(t0, t0, t2);
tcg_gen_shli_tl(t0, t0, 8);
tcg_gen_andi_tl(t0, t0, ~0x00FF00FF00FF00FFULL);
tcg_gen_or_tl(cpu_gpr[rd], t0, t1);
tcg_temp_free(t2);
tcg_temp_free(t1);
}
break;
case OPC_DSHD:
{
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_const_tl(0x0000FFFF0000FFFFULL);
tcg_gen_shri_tl(t1, t0, 16);
tcg_gen_andi_tl(t1, t1, 0x0000FFFF0000FFFFULL);
tcg_gen_and_tl(t1, t1, t2);
tcg_gen_and_tl(t0, t0, t2);
tcg_gen_shli_tl(t0, t0, 16);
tcg_gen_andi_tl(t0, t0, ~0x0000FFFF0000FFFFULL);
tcg_gen_or_tl(t0, t0, t1);
tcg_gen_shri_tl(t1, t0, 32);
tcg_gen_shli_tl(t0, t0, 32);
tcg_gen_or_tl(cpu_gpr[rd], t0, t1);
tcg_temp_free(t2);
tcg_temp_free(t1);
}
break;