From c6c2c0fc32362ba234ae3bdad1a55c2d6aefaa12 Mon Sep 17 00:00:00 2001 From: Pavel Dovgalyuk Date: Fri, 23 Jun 2017 12:41:16 +0200 Subject: [PATCH 1/2] mips: set CP0 Debug DExcCode for SDBBP instruction MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch fixes setting DExcCode field of CP0 Debug register when SDBBP instruction is executed. According to EJTAG specification, this field must be set to the value 9 (Bp). Signed-off-by: Pavel Dovgalyuk Message-id: 20170502120350.3368.92338.stgit@PASHA-ISP Reviewed-by: Aurelien Jarno Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Aurelien Jarno --- target/mips/helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/mips/helper.c b/target/mips/helper.c index e359ca3b44..166f0d1243 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -627,6 +627,8 @@ void mips_cpu_do_interrupt(CPUState *cs) goto set_DEPC; case EXCP_DBp: env->CP0_Debug |= 1 << CP0DB_DBp; + /* Setup DExcCode - SDBBP instruction */ + env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | 9 << CP0DB_DEC; goto set_DEPC; case EXCP_DDBS: env->CP0_Debug |= 1 << CP0DB_DDBS; From 06a57e5cc7ee5292a4915117ebf951e310a28264 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Fri, 23 Jun 2017 12:41:16 +0200 Subject: [PATCH 2/2] target/mips: optimize WSBH, DSBH and DSHD Use the same mask to avoid having to load two different constants. Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target/mips/translate.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index befb87f814..fe44f2f807 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4572,12 +4572,14 @@ static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd) case OPC_WSBH: { TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_const_tl(0x00FF00FF); tcg_gen_shri_tl(t1, t0, 8); - tcg_gen_andi_tl(t1, t1, 0x00FF00FF); + tcg_gen_and_tl(t1, t1, t2); + tcg_gen_and_tl(t0, t0, t2); tcg_gen_shli_tl(t0, t0, 8); - tcg_gen_andi_tl(t0, t0, ~0x00FF00FF); tcg_gen_or_tl(t0, t0, t1); + tcg_temp_free(t2); tcg_temp_free(t1); tcg_gen_ext32s_tl(cpu_gpr[rd], t0); } @@ -4592,27 +4594,31 @@ static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd) case OPC_DSBH: { TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_const_tl(0x00FF00FF00FF00FFULL); tcg_gen_shri_tl(t1, t0, 8); - tcg_gen_andi_tl(t1, t1, 0x00FF00FF00FF00FFULL); + tcg_gen_and_tl(t1, t1, t2); + tcg_gen_and_tl(t0, t0, t2); tcg_gen_shli_tl(t0, t0, 8); - tcg_gen_andi_tl(t0, t0, ~0x00FF00FF00FF00FFULL); tcg_gen_or_tl(cpu_gpr[rd], t0, t1); + tcg_temp_free(t2); tcg_temp_free(t1); } break; case OPC_DSHD: { TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_const_tl(0x0000FFFF0000FFFFULL); tcg_gen_shri_tl(t1, t0, 16); - tcg_gen_andi_tl(t1, t1, 0x0000FFFF0000FFFFULL); + tcg_gen_and_tl(t1, t1, t2); + tcg_gen_and_tl(t0, t0, t2); tcg_gen_shli_tl(t0, t0, 16); - tcg_gen_andi_tl(t0, t0, ~0x0000FFFF0000FFFFULL); tcg_gen_or_tl(t0, t0, t1); tcg_gen_shri_tl(t1, t0, 32); tcg_gen_shli_tl(t0, t0, 32); tcg_gen_or_tl(cpu_gpr[rd], t0, t1); + tcg_temp_free(t2); tcg_temp_free(t1); } break;