Mitchell Horne 134f7b5fa9 riscv: improve commentary around initial stvec ... Make it explicit why we must set the trap vector before enabling virtual memory. Reviewed by: br, jhb, markj Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D45474		2024-06-14 15:02:05 -03:00
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allwinner	sys: Remove $FreeBSD$: one-line sh pattern	2023-08-16 11:54:58 -06:00
conf	riscv: include ahci device to GENERIC.	2024-06-12 13:40:50 +01:00
include	riscv: add stage 2 translation to pmap.	2024-06-05 14:36:57 +01:00
riscv	riscv: improve commentary around initial stvec	2024-06-14 15:02:05 -03:00
sifive	fu740_pci_dw: Fix PERST delay and keep asserted for rest of reset sequence	2024-06-02 21:42:18 +01:00
starfive	jh7110: Add StarFive JH7110 clock/reset generator drivers	2024-05-07 13:07:36 -03:00