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riscv: improve commentary around initial stvec
Make it explicit why we must set the trap vector before enabling virtual memory. Reviewed by: br, jhb, markj Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D45474
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@ -197,7 +197,11 @@ pagetables:
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/* Page tables END */
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/* Setup supervisor trap vector */
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/*
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* Set the supervisor trap vector temporarily. Enabling virtual memory
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* may generate a page fault. We simply wish to continue onwards, so
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* have the trap deliver us to 'va'.
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*/
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2:
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lla t0, va
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sub t0, t0, s9
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@ -221,7 +225,7 @@ va:
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lla gp, __global_pointer$
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.option pop
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/* Setup supervisor trap vector */
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/* Set the trap vector to the real handler. */
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la t0, cpu_exception_handler
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csrw stvec, t0
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@ -342,7 +346,11 @@ ENTRY(mpentry)
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/* Get the kernel's load address */
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jal get_physmem
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/* Setup supervisor trap vector */
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/*
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* Set the supervisor trap vector temporarily. Enabling virtual memory
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* may generate a page fault. We simply wish to continue onwards, so
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* have the trap deliver us to 'mpva'.
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*/
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lla t0, mpva
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sub t0, t0, s9
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li t1, KERNBASE
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@ -365,7 +373,7 @@ mpva:
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lla gp, __global_pointer$
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.option pop
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/* Setup supervisor trap vector */
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/* Set the trap vector to the real handler. */
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la t0, cpu_exception_handler
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csrw stvec, t0
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