serenity/Kernel/Arch/x86
Linus Groh 20e2e39fcc Kernel: Expose size of L1 data/instruction, L2, and L3 CPU caches :^)
These are added as properties of the "caches" object to each processor,
if available.
2022-05-29 15:23:57 +02:00
..
common Kernel: Expose size of L1 data/instruction, L2, and L3 CPU caches :^) 2022-05-29 15:23:57 +02:00
i386 Kernel: Remove unnecessary includes from Thread.h 2022-01-30 16:21:59 +01:00
x86_64 Kernel: Set CS selector when initializing thread context on x86_64 2022-02-27 00:38:00 +02:00
ASM_wrapper.h Kernel: Add helpers for rdrand and rdseed 2022-03-21 23:33:42 +01:00
CPU.h Kernel: Make handle_crash available to aarch64 2022-04-02 19:34:20 -07:00
CPUID.h Kernel: Rename OSPKU CPUID feature flag to OSPKE 2022-04-08 18:53:42 +01:00
DescriptorTable.h Kernel: Use enum instead of magic numbers for GDT descriptor types 2022-01-04 19:08:07 +02:00
InterruptDisabler.h Kernel: Add an x86 include check+error in x86/InerruptDisabler.h 2021-12-01 11:22:04 -08:00
Interrupts.h Kernel/Interrupts: Initialize two spurious handlers when PIC is disabled 2022-01-30 21:07:20 +02:00
IO.h Everywhere: Run clang-format 2022-04-01 21:24:45 +01:00
ISRStubs.h Kernel/Interrupts: Initialize two spurious handlers when PIC is disabled 2022-01-30 21:07:20 +02:00
linker.ld Kernel: Move aarch64 Prekernel into Kernel 2022-03-12 14:54:12 -08:00
mcontext.h Kernel: Add support for SA_SIGINFO 2022-03-04 20:07:05 +01:00
MSR.h Kernel: Add an x86 include check+error in x86/MSR.h 2021-12-01 11:22:04 -08:00
Processor.h Kernel: Implement AVX XSAVE support 2022-05-15 12:25:23 +02:00
ProcessorInfo.h Kernel: Expose size of L1 data/instruction, L2, and L3 CPU caches :^) 2022-05-29 15:23:57 +02:00
RegisterState.h Everywhere: Run clang-format 2022-04-01 21:24:45 +01:00
SIMDState.h Kernel: Implement AVX XSAVE support 2022-05-15 12:25:23 +02:00
TrapFrame.h Everywhere: Run clang-format 2022-04-01 21:24:45 +01:00
TSS.h Everywhere: Run clang-format 2022-04-01 21:24:45 +01:00