Commit graph

1071 commits

Author SHA1 Message Date
Sönke Holz de02a2680f Kernel/riscv64: Handle breakpoint traps
This means that userspace breakpoint traps no longer panic the kernel.
This also causes us to no longer panic on failed assertions in userspace
when using gcc, as gcc compiles __builtin_trap to breakpoint
instructions on RISC-V.
2024-05-23 14:11:36 -06:00
Liav A. c48d540230 Kernel: Move VGATextModeConsole code to the Arch/x86_64/ISABus directory
This code is specific to x86 machines, as virtually no other computer
architecture has any compatibility with old VGA legacy functionality.
2024-05-23 05:07:56 -06:00
Idan Horowitz 26cff62a0a Kernel: Rename Memory::PhysicalPage to Memory::PhysicalRAMPage
Since these are now only used to represent RAM pages, (and not MMIO
pages) rename them to make their purpose more obvious.
2024-05-17 15:38:28 -06:00
Idan Horowitz 827322c139 Kernel: Stop allocating physical pages for mapped MMIO regions
As MMIO is placed at fixed physical addressed, and does not need to be
backed by real RAM physical pages, there's no need to use PhysicalPage
instances to track their pages.
This results in slightly reduced allocations, but more importantly
makes MMIO addresses which end up after the normal RAM ranges work,
like 64-bit PCI BARs usually are.
2024-05-17 15:38:28 -06:00
Liav A. e1d435d0b0 Kernel/x86_64: Rename PCI HostBridge => PIIX4HostBridge
This code is actually for the old PIIX4 PCI host bridge, which requires
to use legacy x86 IO instructions.
2024-05-14 15:42:29 -06:00
Liav A 6014ce0552 Kernel/PCI: Add small access spinlock to each HostController
Prepare to remove biglock on PCI::Access in a future commit, so we can
ensure we only lock a spinlock on a precise PCI HostController if needed
instead of the entire subsystem.
2024-05-14 15:42:29 -06:00
Liav A d068af89d5 Kernel/x86: Bake the Prekernel and the Kernel into one image
The new baked image is a Prekernel and a Kernel baked together now, so
essentially we no longer need to pass the Prekernel as -kernel and the
actual kernel image as -initrd to QEMU, leaving the option to pass an
actual initrd or initramfs module later on with multiboot.
2024-05-14 23:37:38 +02:00
Sönke Holz fe12a413a1 Kernel: Use AK::unwind_stack_from_frame_pointer 2024-05-14 14:02:06 -06:00
Liav A. 2cb86c1309 Kernel/Storage: Remove ATA IDE support
Nobody uses this functionality. I used this code on my old 2007 ICH7
test machine about a year ago, but bare metal is a small aspect of the
project, so it's safe to assume that nobody really tests this piece of
code.
Therefore, let's drop this for good and focus on more modern hardware.
2024-05-14 12:38:05 -06:00
implicitfield a08d1637e2 Kernel: Add FUSE support
This adds both the fuse device (used for communication between the
kernel and the filesystem) and filesystem implementation itself.
2024-05-07 16:54:27 -06:00
Hendiadyoin1 b17f080dcc Kernel/riscv: Use new DeviceTree helpers in PCI initializations
This also changes the PCI interface slightly to be a bit nicer to work
with.
2024-05-02 07:44:13 -06:00
Sönke Holz b363abb082 Kernel/aarch64: Explicitly allow float instrs in {load,store}_fpu_state
LLVM 18 otherwise throws errors, as we use '-mgeneral-regs-only' in the
kernel.
The functions had to be moved into a .S, as there is no
'-mno-general-regs-only' and also no nice way to remove
'-mgeneral-regs-only' for a single .cpp file.
2024-04-30 06:32:58 -06:00
Idan Horowitz dfa2c98497 Kernel: Support the RISC-V PLIC
By supporting the RISC-V PLIC (Platform-Level Interrupt Controller)
we can now handle device (external) interrupts.
2024-04-30 06:01:26 -06:00
Idan Horowitz 0a2d520b15 Kernel: Handle CLINT interrupts separately from normal interrupts
Since CLINT interrupts are wired directly into the hart, instead of
going through an interrupt controller (the PLIC), trying to handle them
through the normal numbered-interrupt mechanism will just complicate it
for no reason.
Instead we now handle them directly in the trap handler.
2024-04-30 06:01:26 -06:00
Idan Horowitz 002bba4a97 Kernel: Configure PCI interrupt routing based on the FDT 2024-04-30 06:01:26 -06:00
Idan Horowitz 7102d90b2b Kernel: Verify we are running on hart 0
This is already an implicit assumption when we initialize our CPU id.
2024-04-30 06:01:26 -06:00
Idan Horowitz d3e285c253 Kernel: Deduplicate HardwareTimerBase::frequency()/ticks_per_second() 2024-04-30 06:01:26 -06:00
Liav A. 2bba9411ca Kernel: Use the AK SetOnce container class in various cases
We have many places in the kernel code that we have boolean flags that
are only set once, and never reset again but are checked multiple times
before and after the time they're being set, which matches the purpose
of the SetOnce class.
2024-04-26 23:46:23 -06:00
Sönke Holz 01f1d2daaa Kernel/riscv64: Don't clobber the boot info argument in enable_paging
"register asm" variables don't preserve the register value, so the call
to calculate_physical_to_link_time_address_offset in the asm input
operands is allowed to clobber a0.
2024-04-26 15:01:31 -06:00
Idan Horowitz 543fc4d0fc Kernel: Support automatic configuration of PCI bridges based on the FDT
This let's us actually boot with RISC-V.
2024-04-26 09:52:56 +02:00
Timothy Flynn fecd08ce64 Everywhere: Remove 'clang-format off' comments that are no longer needed 2024-04-24 16:50:01 -04:00
Timothy Flynn ec492a1a08 Everywhere: Run clang-format
The following command was used to clang-format these files:

    clang-format-18 -i $(find . \
        -not \( -path "./\.*" -prune \) \
        -not \( -path "./Base/*" -prune \) \
        -not \( -path "./Build/*" -prune \) \
        -not \( -path "./Toolchain/*" -prune \) \
        -not \( -path "./Ports/*" -prune \) \
        -type f -name "*.cpp" -o -name "*.mm" -o -name "*.h")

There are a couple of weird cases where clang-format now thinks that a
pointer access in an initializer list, e.g. `m_member(ptr->foo)`, is a
lambda return statement, and it puts spaces around the `->`.
2024-04-24 16:50:01 -04:00
Sönke Holz 511e411def Kernel/riscv64: Implement Processor::read_cpu_counter
This simply reads the current cycle count from the cycle CSR.
x86-64 uses the similar rdtsc instruction here, which also may or may
not tick at a constant rate.
2024-04-21 13:37:32 -06:00
Sönke Holz c57e39d52b Kernel/riscv64: Don't flush the entire TLB in Processor::flush_tlb_local 2024-04-21 13:37:06 -06:00
Sönke Holz 243d7003a2 Kernel+LibC+LibELF: Move TLS handling to userspace
This removes the allocate_tls syscall and adds an archctl option to set
the fs_base for the current thread on x86-64, since you can't set that
register from userspace. enter_thread_context loads the fs_base for the
next thread on each context switch.
This also moves tpidr_el0 (the thread pointer register on AArch64) to
the register state, so it gets properly saved/restored on context
switches.

The userspace TLS allocation code is kept pretty similar to the original
kernel TLS code, aside from a couple of style changes.

We also have to add a new argument "tls_pointer" to
SC_create_thread_params, as we otherwise can't prevent race conditions
between setting the thread pointer register and signal handling code
that might be triggered before the thread pointer was set, which could
use TLS.
2024-04-19 16:46:47 -06:00
Sönke Holz 216089c7a1 Kernel: Add a Thread member for arch-specific data
This will be used to store the fs_base value on x86-64, which is needed
for thread-local storage.
2024-04-19 16:46:47 -06:00
Sönke Holz 57f4f8caf8 Kernel+LibC: Introduce new archctl syscall
This syscall will be used for architecture-specific operations.
2024-04-19 16:46:47 -06:00
Dan Klishch 5ed7cd6e32 Everywhere: Use east const in more places
These changes are compatible with clang-format 16 and will be mandatory
when we eventually bump clang-format version. So, since there are no
real downsides, let's commit them now.
2024-04-19 06:31:19 -04:00
Sönke Holz 6cd130ec8e Kernel/riscv64: Increment sepc before re-enabling interrupts
This otherwise caused a race condition between the signal dispatcher
(which sets sepc to the signal trampoline) and sepc being updated in the
trap handler.
We obviously have to keep the sepc set by the signal dispatcher and not
increment it afterwards.
2024-04-17 11:24:34 -06:00
Space Meyer fdc0328ce3 Kernel: Exclude individual functions from coverage instrumentation
Sticking this to the function source has multiple benefits:
- We instrument more code, by not excluding entire files.
- NO_SANITIZE_COVERAGE can be used in Header files.
- Keeping the info with the source code, means if a function or
  file is moved around, the NO_SANITIZE_COVERAGE moves with it.
2024-04-15 21:16:22 -06:00
Space Meyer ca89116a46 Kernel: Only build kcov object files, if feature is enabled 2024-04-15 21:16:22 -06:00
Sönke Holz ec5cfc031e Kernel/riscv64: Add Linux boot header
This allows us to boot via U-Boot's booti command.
2024-03-25 14:30:39 -06:00
Sönke Holz 1a312f4265 Kernel/riscv64: Only enable interrupts in trap handler if they were on
Always enabling interrupts is in hindsight obviously a bug, as trapping
code that has interrupts disabled very likely expects that they stay
disabled.
2024-03-25 14:21:41 -06:00
Sönke Holz 6a223c6210 Kernel/riscv64: Set g_total_processors to a hard-coded value of 1
This value is used by the NVMe driver to determine the number of queues
to create.
2024-03-25 14:20:39 -06:00
Sönke Holz 58a2e6412c Kernel/riscv64: Implement Processor::pause 2024-03-25 14:20:39 -06:00
Sönke Holz 040e0fe88c Kernel/riscv64: Implement microseconds_delay
This simple delay loop uses the time CSR to wait for the given amount
of time. The tick frequency of the CSR is read from the
/cpus/timebase-frequency devicetree property.
2024-03-25 14:20:39 -06:00
Sönke Holz 6654021655 Kernel/riscv64: Don't hard-code the page fault reason on RISC-V
Instead, rewrite the region page fault handling code to not use
PageFault::type() on RISC-V.

I split Region::handle_fault into having a RISC-V-specific
implementation, as I am not sure if I cover all page fault handling edge
cases by solely relying on MM's own region metadata.
We should probably also take the processor-provided page fault reason
into account, if we decide to merge these two implementations in the
future.
2024-03-25 14:18:38 -06:00
Sönke Holz 66f8d0f031 Kernel/riscv64: Add support for handling traps from userspace
This commit also removes the unnecessary user_sp RegisterState member.
We never use the kernel stack pointer on entry, so we can simply always
store the stack pointer of the previous privilege mode in sp.

Also remove the sp member from mcontext, as RISC-V doesn't have a
dedicated stack pointer register.
sp is defined to be x2 (x[1] in our case) by the ABI.

I probably accidentally included sp while copying the struct from
aarch64.
2024-03-25 14:14:43 -06:00
Sönke Holz afe9a12412 Kernel/riscv64: Handle syscalls
sepc has to be incremented before the call to syscall_handler,
as we otherwise would return to the ecall instruction, resulting in an
infinite trap loop.
We can't increment it after syscall_handler, as sepc might get changed
while handling the syscall.
2024-03-25 14:11:43 -06:00
Sönke Holz 378fa09a5a Kernel/riscv64: Fix typo (CSR::SATP::Mode::{Sv67 => Sv57}) 2024-03-20 10:36:10 -06:00
Hendiadyoin1 53dd04e219 Kernel/riscv64: Read the timebase-frequency from the device tree 2024-02-24 16:43:44 -07:00
Hendiadyoin1 3941277940 Kernel/riscv64: Get the kernel command line from the device tree
This also hides the fdt dump by default now,
it can be activated by adding `dump_fdt` to the kernel command line
2024-02-24 16:43:44 -07:00
Hendiadyoin1 a99bd8eda6 Kernel/riscv64: Initialize PCI controllers using the device tree
Currently the search path is limited to `/soc/pci*` but this is enough
to get it to work on qemu.
2024-02-24 16:43:44 -07:00
Hediadyoin1 7309427d2f Kernel/riscv64: Unflatten the DeviceTree 2024-02-24 16:43:44 -07:00
Hendiadyoin1 d3f6b03733 Kernel/riscv64: Take the memory map from the FDT and dump it
For this the BootInfo struct was made architecture specific
2024-02-24 16:43:44 -07:00
Sönke Holz 1fc0c84017 Kernel/riscv64: Implement Processor::assume_context
This code is based on the aarch64 implementation.
2024-02-24 16:42:58 -07:00
Sönke Holz 726865592c Kernel/riscv64: Implement Processor::switch_context
This code is based on the aarch64 implementation.
2024-02-24 16:42:58 -07:00
Sönke Holz 494e026ca7 Kernel/riscv64: Implement Processor::init_context
This code is based on the aarch64 implementation.
2024-02-24 16:42:58 -07:00
Sönke Holz efdc433ebc Kernel/riscv64: Implement thread_context_first_enter
thread_context_first_enter reuses the context restoring code in the
trap handler, just like other arches already do.

The `ld x2, 1*8(sp)` is unnecessary in the trap handler, as the stack
pointer should be equal to the stack pointer slot in the RegisterState
if the trap is from supervisor mode (and we currently don't support
user traps).
This load will however make us unable to reuse that code for
thread_context_first_enter.
2024-02-24 16:42:58 -07:00
Sönke Holz 7fbcceb657 Kernel/riscv64: Implement enter_thread_context
This code is based on the aarch64 implementation.
2024-02-24 16:42:58 -07:00