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https://github.com/SerenityOS/serenity
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Kernel: Support automatic configuration of PCI bridges based on the FDT
This let's us actually boot with RISC-V.
This commit is contained in:
Idan Horowitz
Andreas Kling
parent
08d4b231e1
commit
543fc4d0fc
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@ -52,6 +52,10 @@ void initialize()
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[[maybe_unused]] auto soc_size_cells = soc.get_property("#size-cells"sv).value().as<u32>();
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Optional<u32> domain_counter;
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Optional<FlatPtr> pci_32bit_mmio_base;
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u32 pci_32bit_mmio_size = 0;
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Optional<FlatPtr> pci_64bit_mmio_base;
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u64 pci_64bit_mmio_size = 0;
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for (auto const& entry : soc.children()) {
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if (!entry.key.starts_with("pci"sv))
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continue;
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@ -147,8 +151,53 @@ void initialize()
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case ControllerCompatible::Unknown:
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VERIFY_NOT_REACHED(); // This should have been rejected earlier
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}
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auto maybe_ranges = node.get_property("ranges"sv);
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if (maybe_ranges.has_value()) {
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auto address_cells = node.get_property("#address-cells"sv).value().as<u32>();
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VERIFY(address_cells == 3); // Additional cell for OpenFirmware PCI address metadata
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auto size_cells = node.get_property("#size-cells"sv).value().as<u32>();
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auto stream = maybe_ranges.value().as_stream();
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while (!stream.is_eof()) {
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u32 pci_address_metadata = MUST(stream.read_value<BigEndian<u32>>());
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FlatPtr pci_address = MUST(stream.read_value<BigEndian<u64>>());
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FlatPtr mmio_address;
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if (soc_address_cells == 1)
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mmio_address = MUST(stream.read_value<BigEndian<u32>>());
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else
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mmio_address = MUST(stream.read_value<BigEndian<u64>>());
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u64 mmio_size;
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if (size_cells == 1)
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mmio_size = MUST(stream.read_value<BigEndian<u32>>());
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else
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mmio_size = MUST(stream.read_value<BigEndian<u64>>());
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auto space_type = (pci_address_metadata >> OpenFirmwareAddress::space_type_offset) & OpenFirmwareAddress::space_type_mask;
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if (space_type != OpenFirmwareAddress::SpaceType::Memory32BitSpace && space_type != OpenFirmwareAddress::SpaceType::Memory64BitSpace)
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continue; // We currently only support memory-mapped PCI on RISC-V
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// TODO: Support mapped PCI addresses
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VERIFY(pci_address == mmio_address);
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if (space_type == OpenFirmwareAddress::SpaceType::Memory32BitSpace) {
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auto prefetchable = (pci_address_metadata >> OpenFirmwareAddress::prefetchable_offset) & OpenFirmwareAddress::prefetchable_mask;
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if (prefetchable)
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continue; // We currently only use non-prefetchable 32-bit regions, since 64-bit regions are always prefetchable - TODO: Use 32-bit prefetchable regions if only they are available
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if (pci_32bit_mmio_base.has_value() && pci_32bit_mmio_size >= mmio_size)
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continue; // We currently only use the single largest region - TODO: Use all available regions if needed
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pci_32bit_mmio_base = mmio_address;
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pci_32bit_mmio_size = mmio_size;
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} else {
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if (pci_64bit_mmio_base.has_value() && pci_64bit_mmio_size >= mmio_size)
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continue; // We currently only use the single largest region - TODO: Use all available regions if needed
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pci_64bit_mmio_base = mmio_address;
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pci_64bit_mmio_size = mmio_size;
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}
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}
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}
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}
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if (pci_32bit_mmio_base.has_value() || pci_64bit_mmio_base.has_value())
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Access::the().configure_pci_space(pci_32bit_mmio_base.value_or(0), pci_32bit_mmio_size, pci_64bit_mmio_base.value_or(0), pci_64bit_mmio_size);
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else
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dmesgln("PCI: No MMIO ranges found - assuming pre-configured by bootloader");
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Access::the().rescan_hardware();
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PCIBusSysFSDirectory::initialize();
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@ -154,6 +154,16 @@ UNMAP_AFTER_INIT Access::Access()
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s_access = this;
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}
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UNMAP_AFTER_INIT void Access::configure_pci_space(FlatPtr mmio_32bit_base, u32 mmio_32bit_size, FlatPtr mmio_64bit_base, u64 mmio_64bit_size)
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{
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SpinlockLocker locker(m_access_lock);
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SpinlockLocker scan_locker(m_scan_lock);
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FlatPtr mmio_32bit_end = mmio_32bit_base + mmio_32bit_size;
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FlatPtr mmio_64bit_end = mmio_64bit_base + mmio_64bit_size;
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for (auto& [_, host_controller] : m_host_controllers)
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host_controller->configure_attached_devices(mmio_32bit_base, mmio_32bit_end, mmio_64bit_base, mmio_64bit_end);
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}
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UNMAP_AFTER_INIT void Access::rescan_hardware()
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{
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SpinlockLocker locker(m_access_lock);
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@ -27,6 +27,7 @@ public:
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#endif
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ErrorOr<void> fast_enumerate(Function<void(DeviceIdentifier const&)>&) const;
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void configure_pci_space(FlatPtr mmio_32bit_base, u32 mmio_32bit_size, FlatPtr mmio_64bit_base, u64 mmio_64bit_size);
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void rescan_hardware();
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static Access& the();
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@ -5,6 +5,7 @@
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*/
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#include <AK/Format.h>
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#include <Kernel/Bus/PCI/API.h>
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#include <Kernel/Bus/PCI/Access.h>
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#include <Kernel/Bus/PCI/Controller/HostController.h>
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#include <Kernel/Bus/PCI/Definitions.h>
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@ -45,6 +46,21 @@ UNMAP_AFTER_INIT Vector<Capability> HostController::get_capabilities_for_functio
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return capabilities;
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}
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void HostController::write8_field(BusNumber bus, DeviceNumber device, FunctionNumber function, PCI::RegisterOffset field, u8 value)
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{
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write8_field(bus, device, function, to_underlying(field), value);
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}
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void HostController::write16_field(BusNumber bus, DeviceNumber device, FunctionNumber function, RegisterOffset field, u16 value)
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{
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write16_field(bus, device, function, to_underlying(field), value);
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}
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void HostController::write32_field(BusNumber bus, DeviceNumber device, FunctionNumber function, RegisterOffset field, u32 value)
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{
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write32_field(bus, device, function, to_underlying(field), value);
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}
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u8 HostController::read8_field(BusNumber bus, DeviceNumber device, FunctionNumber function, PCI::RegisterOffset field)
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{
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return read8_field(bus, device, function, to_underlying(field));
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@ -54,7 +70,7 @@ u16 HostController::read16_field(BusNumber bus, DeviceNumber device, FunctionNum
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return read16_field(bus, device, function, to_underlying(field));
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}
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UNMAP_AFTER_INIT void HostController::enumerate_functions(Function<void(EnumerableDeviceIdentifier const&)> const& callback, BusNumber bus, DeviceNumber device, FunctionNumber function, bool recursive_search_into_bridges)
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UNMAP_AFTER_INIT void HostController::enumerate_functions(Function<void(EnumerableDeviceIdentifier const&)> const& callback, Function<void(EnumerableDeviceIdentifier const&)>& post_bridge_callback, BusNumber bus, DeviceNumber device, FunctionNumber function, bool recursive_search_into_bridges)
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{
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dbgln_if(PCI_DEBUG, "PCI: Enumerating function, bus={}, device={}, function={}", bus, device, function);
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Address address(domain_number(), bus.value(), device.value(), function.value());
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@ -70,7 +86,8 @@ UNMAP_AFTER_INIT void HostController::enumerate_functions(Function<void(Enumerab
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InterruptLine interrupt_line = read8_field(bus, device, function, PCI::RegisterOffset::INTERRUPT_LINE);
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InterruptPin interrupt_pin = read8_field(bus, device, function, PCI::RegisterOffset::INTERRUPT_PIN);
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auto capabilities = get_capabilities_for_function(bus, device, function);
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callback(EnumerableDeviceIdentifier { address, id, revision_id, class_code, subclass_code, prog_if, subsystem_id, subsystem_vendor_id, interrupt_line, interrupt_pin, capabilities });
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auto device_ientifier = EnumerableDeviceIdentifier { address, id, revision_id, class_code, subclass_code, prog_if, subsystem_id, subsystem_vendor_id, interrupt_line, interrupt_pin, capabilities };
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callback(device_ientifier);
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if (pci_class == (to_underlying(PCI::ClassID::Bridge) << 8 | to_underlying(PCI::Bridge::SubclassID::PCI_TO_PCI))
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&& recursive_search_into_bridges
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@ -79,32 +96,35 @@ UNMAP_AFTER_INIT void HostController::enumerate_functions(Function<void(Enumerab
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dbgln_if(PCI_DEBUG, "PCI: Found secondary bus: {}", secondary_bus);
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VERIFY(secondary_bus != bus);
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m_enumerated_buses.set(secondary_bus, true);
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enumerate_bus(callback, secondary_bus, recursive_search_into_bridges);
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enumerate_bus(callback, post_bridge_callback, secondary_bus, recursive_search_into_bridges);
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if (post_bridge_callback)
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post_bridge_callback(device_ientifier);
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}
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}
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UNMAP_AFTER_INIT void HostController::enumerate_device(Function<void(EnumerableDeviceIdentifier const&)> const& callback, BusNumber bus, DeviceNumber device, bool recursive_search_into_bridges)
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UNMAP_AFTER_INIT void HostController::enumerate_device(Function<void(EnumerableDeviceIdentifier const&)> const& callback, Function<void(EnumerableDeviceIdentifier const&)>& post_bridge_callback, BusNumber bus, DeviceNumber device, bool recursive_search_into_bridges)
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{
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dbgln_if(PCI_DEBUG, "PCI: Enumerating device in bus={}, device={}", bus, device);
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if (read16_field(bus, device, 0, PCI::RegisterOffset::VENDOR_ID) == PCI::none_value)
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return;
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enumerate_functions(callback, bus, device, 0, recursive_search_into_bridges);
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enumerate_functions(callback, post_bridge_callback, bus, device, 0, recursive_search_into_bridges);
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if (!(read8_field(bus, device, 0, PCI::RegisterOffset::HEADER_TYPE) & 0x80))
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return;
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for (u8 function = 1; function < 8; ++function) {
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if (read16_field(bus, device, function, PCI::RegisterOffset::VENDOR_ID) != PCI::none_value)
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enumerate_functions(callback, bus, device, function, recursive_search_into_bridges);
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enumerate_functions(callback, post_bridge_callback, bus, device, function, recursive_search_into_bridges);
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}
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}
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UNMAP_AFTER_INIT void HostController::enumerate_bus(Function<void(EnumerableDeviceIdentifier const&)> const& callback, BusNumber bus, bool recursive_search_into_bridges)
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UNMAP_AFTER_INIT void HostController::enumerate_bus(Function<void(EnumerableDeviceIdentifier const&)> const& callback, Function<void(EnumerableDeviceIdentifier const&)>& post_bridge_callback, BusNumber bus, bool recursive_search_into_bridges)
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{
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dbgln_if(PCI_DEBUG, "PCI: Enumerating bus {}", bus);
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for (u8 device = 0; device < 32; ++device)
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enumerate_device(callback, bus, device, recursive_search_into_bridges);
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enumerate_device(callback, post_bridge_callback, bus, device, recursive_search_into_bridges);
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}
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UNMAP_AFTER_INIT void HostController::enumerate_attached_devices(Function<void(EnumerableDeviceIdentifier const&)> callback)
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UNMAP_AFTER_INIT void HostController::enumerate_attached_devices(Function<void(EnumerableDeviceIdentifier const&)> callback, Function<void(EnumerableDeviceIdentifier const&)> post_bridge_callback)
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{
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VERIFY(Access::the().access_lock().is_locked());
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VERIFY(Access::the().scan_lock().is_locked());
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@ -112,7 +132,7 @@ UNMAP_AFTER_INIT void HostController::enumerate_attached_devices(Function<void(E
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// First scan bus 0. Find any device on that bus, and if it's a PCI-to-PCI
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// bridge, recursively scan it too.
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m_enumerated_buses.set(m_domain.start_bus(), true);
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enumerate_bus(callback, m_domain.start_bus(), true);
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enumerate_bus(callback, post_bridge_callback, m_domain.start_bus(), true);
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// Handle Multiple PCI host bridges on bus 0, device 0, functions 1-7 (function 0
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// is the main host bridge).
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@ -128,10 +148,124 @@ UNMAP_AFTER_INIT void HostController::enumerate_attached_devices(Function<void(E
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break;
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if (m_enumerated_buses.get(m_domain.start_bus() + bus_as_function_number))
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continue;
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enumerate_bus(callback, m_domain.start_bus() + bus_as_function_number, false);
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enumerate_bus(callback, post_bridge_callback, m_domain.start_bus() + bus_as_function_number, false);
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m_enumerated_buses.set(m_domain.start_bus() + bus_as_function_number, true);
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}
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}
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}
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void HostController::configure_attached_devices(FlatPtr& mmio_32bit_base, FlatPtr mmio_32bit_end, FlatPtr& mmio_64bit_base, FlatPtr mmio_64bit_end)
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{
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// First, Assign PCI-to-PCI bridge bus numbering
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u8 bus_id = 0;
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enumerate_attached_devices([this, &bus_id](EnumerableDeviceIdentifier const& device_identifier) {
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// called for each PCI device encountered (including bridges)
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if (read8_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), PCI::RegisterOffset::CLASS) != PCI::ClassID::Bridge)
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return;
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if (read8_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), PCI::RegisterOffset::SUBCLASS) != PCI::Bridge::SubclassID::PCI_TO_PCI)
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return;
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write8_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), PCI::RegisterOffset::SECONDARY_BUS, ++bus_id);
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write8_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), PCI::RegisterOffset::SUBORDINATE_BUS, 0xFF); },
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[this, &bus_id](EnumerableDeviceIdentifier const& device_identifier) {
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// called after a bridge was recursively enumerated
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write8_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), PCI::RegisterOffset::SUBORDINATE_BUS, bus_id);
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});
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// Second, Assign BAR addresses
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// TODO: We currently naively assign addresses bump-allocator style - Switch to a proper allocator if this is not good enough
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enumerate_attached_devices([this, &mmio_32bit_base, mmio_32bit_end, &mmio_64bit_base, mmio_64bit_end](EnumerableDeviceIdentifier const& device_identifier) {
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// device-generic handling
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auto header_type = read8_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), PCI::RegisterOffset::HEADER_TYPE);
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auto const max_bar = (header_type == 0) ? RegisterOffset::BAR5 : RegisterOffset::BAR1;
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for (u32 bar_offset = to_underlying(RegisterOffset::BAR0); bar_offset <= to_underlying(max_bar); bar_offset += 4) {
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auto bar_value = read32_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), bar_offset);
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auto bar_space_type = get_BAR_space_type(bar_value);
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auto bar_prefetchable = (bar_value >> 3) & 1;
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if (bar_space_type != BARSpaceType::Memory32BitSpace && bar_space_type != BARSpaceType::Memory64BitSpace)
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continue; // We only support memory-mapped BAR configuration at the moment
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if (bar_space_type == BARSpaceType::Memory32BitSpace) {
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write32_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), bar_offset, 0xFFFFFFFF);
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auto bar_size = read32_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), bar_offset);
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write32_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), bar_offset, bar_value);
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bar_size &= bar_address_mask;
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bar_size = (~bar_size) + 1;
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if (bar_size == 0)
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continue;
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auto mmio_32bit_address = align_up_to(mmio_32bit_base, bar_size);
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if (mmio_32bit_address + bar_size <= mmio_32bit_end) {
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write32_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), bar_offset, mmio_32bit_address);
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mmio_32bit_base = mmio_32bit_address + bar_size;
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continue;
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}
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auto mmio_64bit_address = align_up_to(mmio_64bit_base, bar_size);
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if (bar_prefetchable && mmio_64bit_address + bar_size <= mmio_64bit_end && mmio_64bit_address + bar_size <= NumericLimits<u32>::max()) {
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write32_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), bar_offset, mmio_64bit_address);
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mmio_64bit_base = mmio_64bit_address + bar_size;
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continue;
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}
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dmesgln("PCI: Ran out of 32-bit MMIO address space");
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VERIFY_NOT_REACHED();
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}
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// 64-bit space
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auto next_bar_value = read32_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), bar_offset + 4);
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write32_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), bar_offset, 0xFFFFFFFF);
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write32_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), bar_offset + 4, 0xFFFFFFFF);
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u64 bar_size = read32_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), bar_offset);
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bar_size |= (u64)read32_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), bar_offset + 4) << 32;
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write32_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), bar_offset, bar_value);
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write32_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), bar_offset + 4, next_bar_value);
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bar_size &= bar_address_mask;
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bar_size = (~bar_size) + 1;
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if (bar_size == 0) {
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bar_offset += 4;
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continue;
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}
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auto mmio_64bit_address = align_up_to(mmio_64bit_base, bar_size);
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if (bar_prefetchable && mmio_64bit_address + bar_size <= mmio_64bit_end) {
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write32_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), bar_offset, mmio_64bit_address & 0xFFFFFFFF);
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write32_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), bar_offset + 4, mmio_64bit_address >> 32);
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mmio_64bit_base = mmio_64bit_address + bar_size;
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bar_offset += 4;
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continue;
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}
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auto mmio_32bit_address = align_up_to(mmio_32bit_base, bar_size);
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if (mmio_32bit_address + bar_size <= mmio_32bit_end) {
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write32_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), bar_offset, mmio_32bit_address & 0xFFFFFFFF);
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write32_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), bar_offset + 4, mmio_32bit_address >> 32);
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mmio_32bit_base = mmio_32bit_address + bar_size;
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bar_offset += 4;
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continue;
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}
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dmesgln("PCI: Ran out of 64-bit MMIO address space");
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VERIFY_NOT_REACHED();
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}
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// enable memory space
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auto command_value = read16_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), PCI::RegisterOffset::COMMAND);
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command_value |= 1 << 1; // memory space enable
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write16_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), PCI::RegisterOffset::COMMAND, command_value);
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if (read8_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), PCI::RegisterOffset::CLASS) != PCI::ClassID::Bridge)
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return;
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if (read8_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), PCI::RegisterOffset::SUBCLASS) != PCI::Bridge::SubclassID::PCI_TO_PCI)
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return;
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// bridge-specific handling
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mmio_32bit_base = align_up_to(mmio_32bit_base, MiB);
|
||||
mmio_64bit_base = align_up_to(mmio_64bit_base, MiB);
|
||||
write32_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), PCI::RegisterOffset::MEMORY_BASE, mmio_32bit_base >> 16);
|
||||
write32_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), PCI::RegisterOffset::PREFETCHABLE_MEMORY_BASE, mmio_64bit_base >> 16);
|
||||
write32_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), PCI::RegisterOffset::PREFETCHABLE_MEMORY_BASE_UPPER_32_BITS, mmio_64bit_base >> 32); },
|
||||
[this, &mmio_32bit_base, &mmio_64bit_base](EnumerableDeviceIdentifier const& device_identifier) {
|
||||
// called after a bridge was recursively enumerated
|
||||
mmio_32bit_base = align_up_to(mmio_32bit_base, MiB);
|
||||
mmio_64bit_base = align_up_to(mmio_64bit_base, MiB);
|
||||
write32_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), PCI::RegisterOffset::MEMORY_LIMIT, mmio_32bit_base >> 16);
|
||||
write32_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), PCI::RegisterOffset::PREFETCHABLE_MEMORY_LIMIT, mmio_64bit_base >> 16);
|
||||
write32_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), PCI::RegisterOffset::PREFETCHABLE_MEMORY_LIMIT_UPPER_32_BITS, mmio_64bit_base >> 32);
|
||||
// enable bridging
|
||||
auto command_value = read16_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), PCI::RegisterOffset::COMMAND);
|
||||
command_value |= 1 << 2; // enable forwarding of requests by the bridge
|
||||
write16_field(device_identifier.address().bus(), device_identifier.address().device(), device_identifier.address().function(), PCI::RegisterOffset::COMMAND, command_value);
|
||||
});
|
||||
}
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -31,12 +31,17 @@ public:
|
|||
|
||||
u32 domain_number() const { return m_domain.domain_number(); }
|
||||
|
||||
void enumerate_attached_devices(Function<void(EnumerableDeviceIdentifier const&)> callback);
|
||||
void enumerate_attached_devices(Function<void(EnumerableDeviceIdentifier const&)> callback, Function<void(EnumerableDeviceIdentifier const&)> post_bridge_callback = nullptr);
|
||||
void configure_attached_devices(FlatPtr& mmio_32bit_base, FlatPtr mmio_32bit_end, FlatPtr& mmio_64bit_base, FlatPtr mmio_64bit_end);
|
||||
|
||||
private:
|
||||
void enumerate_bus(Function<void(EnumerableDeviceIdentifier const&)> const& callback, BusNumber, bool recursive_search_into_bridges);
|
||||
void enumerate_functions(Function<void(EnumerableDeviceIdentifier const&)> const& callback, BusNumber, DeviceNumber, FunctionNumber, bool recursive_search_into_bridges);
|
||||
void enumerate_device(Function<void(EnumerableDeviceIdentifier const&)> const& callback, BusNumber bus, DeviceNumber device, bool recursive_search_into_bridges);
|
||||
void enumerate_bus(Function<void(EnumerableDeviceIdentifier const&)> const& callback, Function<void(EnumerableDeviceIdentifier const&)>& post_bridge_callback, BusNumber, bool recursive_search_into_bridges);
|
||||
void enumerate_functions(Function<void(EnumerableDeviceIdentifier const&)> const& callback, Function<void(EnumerableDeviceIdentifier const&)>& post_bridge_callback, BusNumber, DeviceNumber, FunctionNumber, bool recursive_search_into_bridges);
|
||||
void enumerate_device(Function<void(EnumerableDeviceIdentifier const&)> const& callback, Function<void(EnumerableDeviceIdentifier const&)>& post_bridge_callback, BusNumber bus, DeviceNumber device, bool recursive_search_into_bridges);
|
||||
|
||||
void write8_field(BusNumber, DeviceNumber, FunctionNumber, RegisterOffset field, u8 value);
|
||||
void write16_field(BusNumber, DeviceNumber, FunctionNumber, RegisterOffset field, u16 value);
|
||||
void write32_field(BusNumber, DeviceNumber, FunctionNumber, RegisterOffset field, u32 value);
|
||||
|
||||
u8 read8_field(BusNumber, DeviceNumber, FunctionNumber, RegisterOffset field);
|
||||
u16 read16_field(BusNumber, DeviceNumber, FunctionNumber, RegisterOffset field);
|
||||
|
|
|
|||
|
|
@ -39,32 +39,39 @@ enum class BARSpaceType {
|
|||
Memory64BitSpace,
|
||||
};
|
||||
|
||||
enum class RegisterOffset {
|
||||
VENDOR_ID = 0x00, // word
|
||||
DEVICE_ID = 0x02, // word
|
||||
COMMAND = 0x04, // word
|
||||
STATUS = 0x06, // word
|
||||
REVISION_ID = 0x08, // byte
|
||||
PROG_IF = 0x09, // byte
|
||||
SUBCLASS = 0x0a, // byte
|
||||
CLASS = 0x0b, // byte
|
||||
CACHE_LINE_SIZE = 0x0c, // byte
|
||||
LATENCY_TIMER = 0x0d, // byte
|
||||
HEADER_TYPE = 0x0e, // byte
|
||||
BIST = 0x0f, // byte
|
||||
BAR0 = 0x10, // u32
|
||||
BAR1 = 0x14, // u32
|
||||
BAR2 = 0x18, // u32
|
||||
SECONDARY_BUS = 0x19, // byte
|
||||
BAR3 = 0x1C, // u32
|
||||
BAR4 = 0x20, // u32
|
||||
BAR5 = 0x24, // u32
|
||||
SUBSYSTEM_VENDOR_ID = 0x2C, // u16
|
||||
SUBSYSTEM_ID = 0x2E, // u16
|
||||
EXPANSION_ROM_POINTER = 0x30, // u32
|
||||
CAPABILITIES_POINTER = 0x34, // u8
|
||||
INTERRUPT_LINE = 0x3C, // byte
|
||||
INTERRUPT_PIN = 0x3D, // byte
|
||||
enum class RegisterOffset : u32 {
|
||||
VENDOR_ID = 0x00, // word
|
||||
DEVICE_ID = 0x02, // word
|
||||
COMMAND = 0x04, // word
|
||||
STATUS = 0x06, // word
|
||||
REVISION_ID = 0x08, // byte
|
||||
PROG_IF = 0x09, // byte
|
||||
SUBCLASS = 0x0a, // byte
|
||||
CLASS = 0x0b, // byte
|
||||
CACHE_LINE_SIZE = 0x0c, // byte
|
||||
LATENCY_TIMER = 0x0d, // byte
|
||||
HEADER_TYPE = 0x0e, // byte
|
||||
BIST = 0x0f, // byte
|
||||
BAR0 = 0x10, // u32
|
||||
BAR1 = 0x14, // u32
|
||||
BAR2 = 0x18, // u32
|
||||
SECONDARY_BUS = 0x19, // byte
|
||||
SUBORDINATE_BUS = 0x1A, // byte
|
||||
BAR3 = 0x1C, // u32
|
||||
BAR4 = 0x20, // u32
|
||||
MEMORY_BASE = 0x20, // u16
|
||||
MEMORY_LIMIT = 0x22, // u16
|
||||
BAR5 = 0x24, // u32
|
||||
PREFETCHABLE_MEMORY_BASE = 0x24, // u16
|
||||
PREFETCHABLE_MEMORY_LIMIT = 0x26, // u16
|
||||
PREFETCHABLE_MEMORY_BASE_UPPER_32_BITS = 0x28, // u32
|
||||
PREFETCHABLE_MEMORY_LIMIT_UPPER_32_BITS = 0x2C, // u32
|
||||
SUBSYSTEM_VENDOR_ID = 0x2C, // u16
|
||||
SUBSYSTEM_ID = 0x2E, // u16
|
||||
EXPANSION_ROM_POINTER = 0x30, // u32
|
||||
CAPABILITIES_POINTER = 0x34, // u8
|
||||
INTERRUPT_LINE = 0x3C, // byte
|
||||
INTERRUPT_PIN = 0x3D, // byte
|
||||
};
|
||||
|
||||
enum class Limits {
|
||||
|
|
@ -92,6 +99,22 @@ static constexpr u8 msix_table_bir_mask = 0x7;
|
|||
static constexpr u16 msix_table_offset_mask = 0xfff8;
|
||||
static constexpr u16 msix_control_enable = 0x8000;
|
||||
|
||||
namespace OpenFirmwareAddress {
|
||||
|
||||
static constexpr u8 space_type_offset = 24;
|
||||
static constexpr u8 space_type_mask = 0x3;
|
||||
static constexpr u8 prefetchable_offset = 30;
|
||||
static constexpr u8 prefetchable_mask = 0x1;
|
||||
|
||||
enum SpaceType {
|
||||
ConfigurationSpace = 0,
|
||||
IOSpace = 1,
|
||||
Memory32BitSpace = 2,
|
||||
Memory64BitSpace = 3,
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
// Taken from https://pcisig.com/sites/default/files/files/PCI_Code-ID_r_1_11__v24_Jan_2019.pdf
|
||||
enum class ClassID {
|
||||
Legacy = 0x00,
|
||||
|
|
|
|||
Loading…
Reference in a new issue