Frank Chang f714361ed7 target/riscv: rvv-1.0: implement vstart CSR ... * Update and check vstart value for vector instructions. * Add whole register move instruction helper functions as we have to call helper function for case where vstart is not zero. * Remove probe_pages() calls in vector load/store instructions (except fault-only-first loads) to raise the memory access exception at the exact processed vector element. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-67-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-12-20 14:53:31 +10:00
..
insn_trans	target/riscv: rvv-1.0: implement vstart CSR	2021-12-20 14:53:31 +10:00
arch_dump.c
bitmanip_helper.c
cpu-param.h
cpu.c	target/riscv: drop vector 0.7.1 and add 1.0 support	2021-12-20 14:51:36 +10:00
cpu.h	target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits	2021-12-20 14:53:31 +10:00
cpu_bits.h	target/riscv: rvv-1.0: add vlenb register	2021-12-20 14:51:36 +10:00
cpu_helper.c	target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation	2021-12-20 14:51:36 +10:00
cpu_user.h
csr.c	target/riscv: rvv-1.0: implement vstart CSR	2021-12-20 14:53:31 +10:00
fpu_helper.c	target/riscv: add "set round to odd" rounding mode helper function	2021-12-20 14:53:31 +10:00
gdbstub.c
helper.h	target/riscv: rvv-1.0: implement vstart CSR	2021-12-20 14:53:31 +10:00
insn16.decode
insn32.decode	target/riscv: rvv-1.0: narrowing floating-point/integer type-convert	2021-12-20 14:53:31 +10:00
instmap.h
internals.h	target/riscv: add "set round to odd" rounding mode helper function	2021-12-20 14:53:31 +10:00
Kconfig
machine.c
meson.build
monitor.c
op_helper.c
pmp.c
pmp.h
trace-events
trace.h
translate.c	target/riscv: rvv-1.0: implement vstart CSR	2021-12-20 14:53:31 +10:00
vector_helper.c	target/riscv: rvv-1.0: implement vstart CSR	2021-12-20 14:53:31 +10:00