Frank Chang f714361ed7 target/riscv: rvv-1.0: implement vstart CSR ... * Update and check vstart value for vector instructions. * Add whole register move instruction helper functions as we have to call helper function for case where vstart is not zero. * Remove probe_pages() calls in vector load/store instructions (except fault-only-first loads) to raise the memory access exception at the exact processed vector element. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-67-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-12-20 14:53:31 +10:00
..
alpha
arm	target/arm: Correct calculation of tlb range invalidate length	2021-12-15 10:35:26 +00:00
avr
cris
hexagon	target/hexagon/cpu.h: don't include qemu-common.h	2021-12-15 10:35:26 +00:00
hppa
i386	target/i386/kvm: Replace use of __u32 type	2021-12-17 10:40:51 +01:00
m68k
microblaze
mips
nios2
openrisc
ppc	PPC64/TCG: Implement 'rfebb' instruction	2021-12-17 17:57:19 +01:00
riscv	target/riscv: rvv-1.0: implement vstart CSR	2021-12-20 14:53:31 +10:00
rx	target/rx/cpu.h: Don't include qemu-common.h	2021-12-15 10:35:26 +00:00
s390x	s390: kvm: adjust diag318 resets to retain data	2021-12-17 09:12:37 +01:00
sh4
sparc
tricore
xtensa
Kconfig
meson.build