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Andre Przywara b25a83f053 ARM/highbank: add support for Calxeda ECX-2000 / Midway
The Calxeda ECX-2000 chip (aka. Midway) is model-wise quite similar
to the Highbank. The most prominent difference is the Cortex-A15 CPU
core in it, together with the associated core peripherals.

Add a new ARM machine type called "midway".
Move the L2 cache controller device into the Highbank specific part,
since Midway does not have (and need) it.

Signed-off-by: Andre Przywara <andre.przywara@calxeda.com>
Message-id: 1373026897-12085-3-git-send-email-andre.przywara@calxeda.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-07-15 16:25:57 +01:00
audio
backends
block curl: refuse to open URL from HTTP server without range support 2013-07-05 09:40:18 +02:00
bsd-user bsd-user: Change thread_env to CPUState 2013-07-09 21:33:01 +02:00
default-configs pseries: move interrupt controllers to hw/intc/ 2013-07-11 18:51:23 +02:00
disas
docs add a header file for atomic operations 2013-07-04 17:42:49 +02:00
dtc@bc895d6d09
fpu
fsdev fsdev: Fix potential memory leak 2013-07-09 13:38:56 -05:00
gdb-xml
hw ARM/highbank: add support for Calxeda ECX-2000 / Midway 2013-07-15 16:25:57 +01:00
include PPC: dbdma: Support unaligned DMA access 2013-07-11 18:51:25 +02:00
ldscripts
libcacard
linux-headers
linux-user QOM CPUState refactorings 2013-07-10 10:54:16 -05:00
net
pc-bios
pixman@97336fad32
po
qapi
qga
QMP
qobject
qom QOM CPUState refactorings 2013-07-10 10:54:16 -05:00
roms
scripts qapi.py: Allow top-level type reference for command definitions 2013-07-10 13:39:37 -04:00
slirp
stubs
sysconfigs/target
target-alpha target-alpha: Change gen_intermediate_code_internal() argument to AlphaCPU 2013-07-09 21:33:03 +02:00
target-arm cpu: Move reset logging to CPUState 2013-07-09 21:33:04 +02:00
target-cris cpu: Move reset logging to CPUState 2013-07-09 21:33:04 +02:00
target-i386 QOM CPUState refactorings 2013-07-10 10:54:16 -05:00
target-lm32 cpu: Move reset logging to CPUState 2013-07-09 21:33:04 +02:00
target-m68k cpu: Move reset logging to CPUState 2013-07-09 21:33:04 +02:00
target-microblaze cpu: Move reset logging to CPUState 2013-07-09 21:33:04 +02:00
target-mips cpu: Move reset logging to CPUState 2013-07-09 21:33:04 +02:00
target-moxie cpu: Move reset logging to CPUState 2013-07-09 21:33:04 +02:00
target-openrisc cpu: Move reset logging to CPUState 2013-07-09 21:33:04 +02:00
target-ppc target-ppc: Add POWER8 v1.0 CPU model 2013-07-11 18:51:23 +02:00
target-s390x cpu: Move reset logging to CPUState 2013-07-09 21:33:04 +02:00
target-sh4 cpu: Move reset logging to CPUState 2013-07-09 21:33:04 +02:00
target-sparc cpu: Move reset logging to CPUState 2013-07-09 21:33:04 +02:00
target-unicore32 target-unicore32: Change gen_intermediate_code_internal() signature 2013-07-09 21:33:04 +02:00
target-xtensa target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPU 2013-07-09 21:33:04 +02:00
tcg tcg-arm: Implement tcg_register_jit 2013-07-09 07:15:25 -07:00
tests add a header file for atomic operations 2013-07-04 17:42:49 +02:00
trace
ui
util add timestamp to error_report() 2013-07-10 13:42:09 -04:00
.exrc
.gitignore
.gitmodules
.mailmap
aio-posix.c
aio-win32.c
arch_init.c
async.c
balloon.c
block-migration.c
block.c block: fix bdrv_flush() ordering in bdrv_close() 2013-07-05 10:52:23 +02:00
blockdev-nbd.c
blockdev.c
blockjob.c
bt-host.c
bt-vhci.c
Changelog
CODING_STYLE
configure configure: Simplify alternate .text segment 2013-07-09 13:13:20 -05:00
COPYING
COPYING.LIB
coroutine-gthread.c
coroutine-sigaltstack.c
coroutine-ucontext.c
coroutine-win32.c
cpu-exec.c log: Change log_cpu_state[_mask]() argument to CPUState 2013-07-09 21:33:04 +02:00
cpus.c cpu: Make first_cpu and next_cpu CPUState 2013-07-09 21:32:54 +02:00
cputlb.c cpu: Make first_cpu and next_cpu CPUState 2013-07-09 21:32:54 +02:00
device-hotplug.c
device_tree.c vl: Tighten parsing of -machine option phandle_start 2013-07-09 13:38:58 -05:00
disas.c
dma-helpers.c
dump.c cpu: Make first_cpu and next_cpu CPUState 2013-07-09 21:32:54 +02:00
exec.c QOM CPUState refactorings 2013-07-10 10:54:16 -05:00
gdbstub.c cpu: Make first_cpu and next_cpu CPUState 2013-07-09 21:32:54 +02:00
HACKING
hmp-commands.hx
hmp.c
hmp.h
iohandler.c
ioport.c ioport: remove LITTLE_ENDIAN mark for portio 2013-07-12 14:37:47 -05:00
kvm-all.c QOM CPUState refactorings 2013-07-10 10:54:16 -05:00
kvm-stub.c kvm: Change kvm_remove_all_breakpoints() argument to CPUState 2013-07-09 21:20:28 +02:00
LICENSE
main-loop.c
MAINTAINERS tcg: Add myself to general TCG maintainership 2013-07-08 22:03:59 -07:00
Makefile
Makefile.objs
Makefile.target
memory.c cpu: Replace cpu_single_env with CPUState current_cpu 2013-07-09 21:20:28 +02:00
memory_mapping.c cpu: Make first_cpu and next_cpu CPUState 2013-07-09 21:32:54 +02:00
migration-exec.c
migration-fd.c
migration-tcp.c
migration-unix.c
migration.c add a header file for atomic operations 2013-07-04 17:42:49 +02:00
monitor.c cpu: Make first_cpu and next_cpu CPUState 2013-07-09 21:32:54 +02:00
nbd.c
os-posix.c
os-win32.c
page_cache.c
qapi-schema-test.json
qapi-schema.json qapi-schema: Use existing type for drive-backup arguments 2013-07-10 13:39:38 -04:00
qdev-monitor.c
qdict-test-data.txt
qemu-bridge-helper.c
qemu-char.c qemu-char: Fix ringbuf option size 2013-07-10 13:39:37 -04:00
qemu-coroutine-io.c
qemu-coroutine-lock.c
qemu-coroutine-sleep.c
qemu-coroutine.c
qemu-doc.texi
qemu-img-cmds.hx
qemu-img.c
qemu-img.texi
qemu-io-cmds.c
qemu-io.c
qemu-log.c
qemu-nbd.c
qemu-nbd.texi
qemu-options-wrapper.h
qemu-options.h
qemu-options.hx add timestamp to error_report() 2013-07-10 13:42:09 -04:00
qemu-seccomp.c
qemu-tech.texi
qemu-timer.c
qemu.sasl
qmp-commands.hx
qmp.c
qtest.c
readline.c
README
rules.mak
savevm.c
spice-qemu-char.c
tcg-runtime.c
tci.c
thread-pool.c
thunk.c
tpm.c
trace-events
translate-all.c cpu: Make first_cpu and next_cpu CPUState 2013-07-09 21:32:54 +02:00
translate-all.h
user-exec.c QOM CPUState refactorings 2013-07-10 10:54:16 -05:00
VERSION
version.rc
vl.c add timestamp to error_report() 2013-07-10 13:42:09 -04:00
xbzrle.c
xen-all.c
xen-mapcache.c
xen-stub.c

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