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https://gitlab.com/qemu-project/qemu
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e207b4aa71
There is no support for hppa64 in gdb. Any attempt to provide the data for the larger hppa64 registers results in an error from gdb. Mask CR_SAR writes to the width of the register: 5 or 6 bits. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
276 lines
6 KiB
C
276 lines
6 KiB
C
/*
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* HPPA gdb server stub
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*
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* Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "gdbstub/helpers.h"
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/*
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* GDB 15 only supports PA1.0 via the remote protocol, and ignores
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* any provided xml. Which means that any attempt to provide more
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* data results in "Remote 'g' packet reply is too long".
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*/
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int hppa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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{
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CPUHPPAState *env = cpu_env(cs);
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uint32_t val;
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switch (n) {
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case 0:
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val = cpu_hppa_get_psw(env);
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break;
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case 1 ... 31:
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val = env->gr[n];
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break;
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case 32:
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val = env->cr[CR_SAR];
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break;
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case 33:
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val = env->iaoq_f;
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break;
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case 34:
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val = env->iasq_f >> 32;
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break;
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case 35:
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val = env->iaoq_b;
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break;
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case 36:
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val = env->iasq_b >> 32;
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break;
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case 37:
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val = env->cr[CR_EIEM];
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break;
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case 38:
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val = env->cr[CR_IIR];
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break;
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case 39:
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val = env->cr[CR_ISR];
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break;
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case 40:
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val = env->cr[CR_IOR];
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break;
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case 41:
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val = env->cr[CR_IPSW];
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break;
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case 43:
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val = env->sr[4] >> 32;
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break;
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case 44:
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val = env->sr[0] >> 32;
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break;
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case 45:
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val = env->sr[1] >> 32;
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break;
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case 46:
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val = env->sr[2] >> 32;
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break;
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case 47:
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val = env->sr[3] >> 32;
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break;
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case 48:
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val = env->sr[5] >> 32;
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break;
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case 49:
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val = env->sr[6] >> 32;
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break;
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case 50:
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val = env->sr[7] >> 32;
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break;
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case 51:
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val = env->cr[CR_RC];
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break;
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case 52:
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val = env->cr[CR_PID1];
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break;
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case 53:
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val = env->cr[CR_PID2];
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break;
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case 54:
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val = env->cr[CR_SCRCCR];
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break;
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case 55:
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val = env->cr[CR_PID3];
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break;
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case 56:
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val = env->cr[CR_PID4];
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break;
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case 57:
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val = env->cr[24];
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break;
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case 58:
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val = env->cr[25];
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break;
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case 59:
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val = env->cr[26];
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break;
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case 60:
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val = env->cr[27];
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break;
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case 61:
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val = env->cr[28];
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break;
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case 62:
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val = env->cr[29];
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break;
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case 63:
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val = env->cr[30];
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break;
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case 64 ... 127:
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val = extract64(env->fr[(n - 64) / 2], (n & 1 ? 0 : 32), 32);
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break;
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default:
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if (n < 128) {
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val = 0;
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} else {
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return 0;
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}
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break;
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}
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return gdb_get_reg32(mem_buf, val);
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}
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int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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CPUHPPAState *env = cpu_env(cs);
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uint32_t val = ldl_p(mem_buf);
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switch (n) {
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case 0:
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cpu_hppa_put_psw(env, val);
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break;
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case 1 ... 31:
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env->gr[n] = val;
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break;
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case 32:
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env->cr[CR_SAR] = val & (hppa_is_pa20(env) ? 63 : 31);
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break;
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case 33:
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env->iaoq_f = val;
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break;
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case 34:
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env->iasq_f = (uint64_t)val << 32;
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break;
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case 35:
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env->iaoq_b = val;
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break;
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case 36:
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env->iasq_b = (uint64_t)val << 32;
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break;
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case 37:
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env->cr[CR_EIEM] = val;
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break;
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case 38:
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env->cr[CR_IIR] = val;
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break;
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case 39:
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env->cr[CR_ISR] = val;
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break;
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case 40:
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env->cr[CR_IOR] = val;
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break;
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case 41:
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env->cr[CR_IPSW] = val;
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break;
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case 43:
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env->sr[4] = (uint64_t)val << 32;
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break;
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case 44:
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env->sr[0] = (uint64_t)val << 32;
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break;
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case 45:
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env->sr[1] = (uint64_t)val << 32;
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break;
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case 46:
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env->sr[2] = (uint64_t)val << 32;
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break;
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case 47:
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env->sr[3] = (uint64_t)val << 32;
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break;
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case 48:
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env->sr[5] = (uint64_t)val << 32;
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break;
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case 49:
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env->sr[6] = (uint64_t)val << 32;
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break;
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case 50:
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env->sr[7] = (uint64_t)val << 32;
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break;
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case 51:
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env->cr[CR_RC] = val;
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break;
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case 52:
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env->cr[CR_PID1] = val;
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cpu_hppa_change_prot_id(env);
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break;
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case 53:
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env->cr[CR_PID2] = val;
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cpu_hppa_change_prot_id(env);
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break;
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case 54:
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env->cr[CR_SCRCCR] = val;
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break;
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case 55:
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env->cr[CR_PID3] = val;
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cpu_hppa_change_prot_id(env);
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break;
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case 56:
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env->cr[CR_PID4] = val;
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cpu_hppa_change_prot_id(env);
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break;
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case 57:
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env->cr[24] = val;
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break;
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case 58:
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env->cr[25] = val;
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break;
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case 59:
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env->cr[26] = val;
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break;
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case 60:
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env->cr[27] = val;
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break;
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case 61:
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env->cr[28] = val;
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break;
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case 62:
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env->cr[29] = val;
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break;
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case 63:
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env->cr[30] = val;
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break;
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case 64:
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env->fr[0] = deposit64(env->fr[0], 32, 32, val);
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cpu_hppa_loaded_fr0(env);
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break;
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case 65 ... 127:
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{
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uint64_t *fr = &env->fr[(n - 64) / 2];
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*fr = deposit64(*fr, (n & 1 ? 0 : 32), 32, val);
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}
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break;
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default:
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if (n >= 128) {
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return 0;
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}
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break;
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}
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return 4;
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}
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