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Previously not all references mentioned any spec version at all. Given r3.1 is the current specification available for evaluation at www.computeexpresslink.org update references to refer to that. Hopefully this won't become a never ending job. A few structure definitions have been updated to add new fields. Defaults of 0 and read only are valid choices for these new DVSEC registers so go with that for now. There are additional error codes and some of the 'questions' in the comments are resolved now. Update documentation reference to point to the CXL r3.1 specification with naming closer to what is on the cover. For cases where there are structure version numbers, add defines so they can be found next to the register definitions. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240126121636.24611-6-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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| .. | ||
| cxl_downstream.c | ||
| cxl_root_port.c | ||
| cxl_upstream.c | ||
| gen_pcie_root_port.c | ||
| i82801b11.c | ||
| ioh3420.c | ||
| Kconfig | ||
| meson.build | ||
| pci_bridge_dev.c | ||
| pci_expander_bridge.c | ||
| pci_expander_bridge_stubs.c | ||
| pcie_pci_bridge.c | ||
| pcie_root_port.c | ||
| simba.c | ||
| xio3130_downstream.c | ||
| xio3130_upstream.c | ||