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mirror of https://gitlab.com/qemu-project/qemu synced 2024-07-08 20:17:27 +00:00
qemu/target
Daniel Henrique Barboza 944b6dfd3d trans_rvv.c.inc: mark_vs_dirty() before loads and stores
While discussing a problem with how we're (not) setting vstart_eq_zero
Richard had the following to say w.r.t the conditional mark_vs_dirty()
calls on load/store functions [1]:

"I think it's required to have stores set dirty unconditionally, before
the operation.

Consider a store that traps on the 2nd element, leaving vstart = 2, and
exiting to the main loop via exception. The exception enters the kernel
page fault handler. The kernel may need to fault in the page for the
process, and in the meantime task switch.

If vs dirty is not already set, the kernel won't know to save vector
state on task switch."

Do a mark_vs_dirty() before both loads and stores.

[1] https://lore.kernel.org/qemu-riscv/72c7503b-0f43-44b8-aa82-fbafed2aac0c@linaro.org/

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240306171932.549549-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-03-08 20:48:03 +10:00
..
alpha target/alpha: Enable TARGET_PAGE_BITS_VARY for user-only 2024-02-29 11:35:37 -10:00
arm target/arm: Do memory type alignment check when translation enabled 2024-03-05 13:22:56 +00:00
avr gdbstub: Infer number of core registers from XML 2024-02-28 09:09:58 +00:00
cris include/exec: Change cpu_mmu_index argument to CPUState 2024-02-03 16:46:10 +10:00
hexagon gdbstub: Infer number of core registers from XML 2024-02-28 09:09:58 +00:00
hppa target/hppa: Restore unwind_breg before calculating ior 2024-03-03 06:41:19 +01:00
i386 * target/i386: Fix physical address truncation on 32-bit PAE 2024-02-28 14:23:21 +00:00
loongarch target/loongarch: honour show_opcodes when disassembling 2024-03-06 12:35:51 +00:00
m68k gdbstub: Infer number of core registers from XML 2024-02-28 09:09:58 +00:00
microblaze gdbstub: Infer number of core registers from XML 2024-02-28 09:09:58 +00:00
mips target/mips: Remove the unused DisasContext::saar field 2024-02-15 15:53:12 +01:00
nios2 kconfig: use "select" to enable semihosting 2024-02-09 17:52:30 +00:00
openrisc include/exec: Change cpu_mmu_index argument to CPUState 2024-02-03 16:46:10 +10:00
ppc target/ppc: Enable TARGET_PAGE_BITS_VARY for user-only 2024-02-29 11:35:37 -10:00
riscv trans_rvv.c.inc: mark_vs_dirty() before loads and stores 2024-03-08 20:48:03 +10:00
rx gdbstub: Infer number of core registers from XML 2024-02-28 09:09:58 +00:00
s390x gdbstub: Infer number of core registers from XML 2024-02-28 09:09:58 +00:00
sh4 include/exec: Implement cpu_mmu_index generically 2024-02-03 16:46:10 +10:00
sparc accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull 2024-03-05 13:22:56 +00:00
tricore include/exec: Change cpu_mmu_index argument to CPUState 2024-02-03 16:46:10 +10:00
xtensa kconfig: use "select" to enable semihosting 2024-02-09 17:52:30 +00:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target: Make qemu_target_page_mask() available for *-user 2024-01-29 21:04:10 +10:00
target-common.c target: Make qemu_target_page_mask() available for *-user 2024-01-29 21:04:10 +10:00