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94452ac4cf
While testing some changes to GDB's handling for the RISC-V registers fcsr, fflags, and frm, I spotted that QEMU includes these registers twice in the target description it sends to GDB, once in the fpu feature, and once in the csr feature. Right now things basically work OK, QEMU maps these registers onto two different register numbers, e.g. fcsr maps to both 68 and 73, and GDB can use either of these to access the register. However, GDB's target descriptions don't really work this way, each register should appear just once in a target description, mapping the register name onto the number GDB should use when accessing the register on the target. Duplicate register names actually result in duplicate registers on the GDB side, however, as the registers have the same name, the user can only access one of these registers. Currently GDB has a hack in place, specifically for RISC-V, to spot the duplicate copies of these three registers, and hide them from the user, ensuring the user only ever sees a single copy of each. In this commit I propose fixing this issue on the QEMU side, and in the process, simplify the fpu register handling a little. I think we should, remove fflags, frm, and fcsr from the two (32-bit and 64-bit) fpu feature xml files. These files will only contain the 32 core floating point register f0 to f31. The fflags, frm, and fcsr registers will continue to be advertised in the csr feature as they currently are. With that change made, I will simplify riscv_gdb_get_fpu and riscv_gdb_set_fpu, removing the extra handling for the 3 status registers. Signed-off-by: Andrew Burgess <aburgess@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <0fbf2a5b12e3210ff3867d5cf7022b3f3462c9c8.1661934573.git.aburgess@redhat.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
53 lines
2.3 KiB
XML
53 lines
2.3 KiB
XML
<?xml version="1.0"?>
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<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved. -->
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<!-- Register numbers are hard-coded in order to maintain backward
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compatibility with older versions of tools that didn't use xml
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register descriptions. -->
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<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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<feature name="org.gnu.gdb.riscv.fpu">
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<union id="riscv_double">
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<field name="float" type="ieee_single"/>
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<field name="double" type="ieee_double"/>
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</union>
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<reg name="ft0" bitsize="64" type="riscv_double" regnum="33"/>
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<reg name="ft1" bitsize="64" type="riscv_double"/>
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<reg name="ft2" bitsize="64" type="riscv_double"/>
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<reg name="ft3" bitsize="64" type="riscv_double"/>
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<reg name="ft4" bitsize="64" type="riscv_double"/>
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<reg name="ft5" bitsize="64" type="riscv_double"/>
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<reg name="ft6" bitsize="64" type="riscv_double"/>
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<reg name="ft7" bitsize="64" type="riscv_double"/>
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<reg name="fs0" bitsize="64" type="riscv_double"/>
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<reg name="fs1" bitsize="64" type="riscv_double"/>
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<reg name="fa0" bitsize="64" type="riscv_double"/>
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<reg name="fa1" bitsize="64" type="riscv_double"/>
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<reg name="fa2" bitsize="64" type="riscv_double"/>
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<reg name="fa3" bitsize="64" type="riscv_double"/>
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<reg name="fa4" bitsize="64" type="riscv_double"/>
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<reg name="fa5" bitsize="64" type="riscv_double"/>
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<reg name="fa6" bitsize="64" type="riscv_double"/>
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<reg name="fa7" bitsize="64" type="riscv_double"/>
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<reg name="fs2" bitsize="64" type="riscv_double"/>
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<reg name="fs3" bitsize="64" type="riscv_double"/>
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<reg name="fs4" bitsize="64" type="riscv_double"/>
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<reg name="fs5" bitsize="64" type="riscv_double"/>
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<reg name="fs6" bitsize="64" type="riscv_double"/>
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<reg name="fs7" bitsize="64" type="riscv_double"/>
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<reg name="fs8" bitsize="64" type="riscv_double"/>
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<reg name="fs9" bitsize="64" type="riscv_double"/>
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<reg name="fs10" bitsize="64" type="riscv_double"/>
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<reg name="fs11" bitsize="64" type="riscv_double"/>
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<reg name="ft8" bitsize="64" type="riscv_double"/>
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<reg name="ft9" bitsize="64" type="riscv_double"/>
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<reg name="ft10" bitsize="64" type="riscv_double"/>
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<reg name="ft11" bitsize="64" type="riscv_double"/>
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</feature>
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