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Andrew Burgess 94452ac4cf target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml 
While testing some changes to GDB's handling for the RISC-V registers
fcsr, fflags, and frm, I spotted that QEMU includes these registers
twice in the target description it sends to GDB, once in the fpu
feature, and once in the csr feature.

Right now things basically work OK, QEMU maps these registers onto two
different register numbers, e.g. fcsr maps to both 68 and 73, and GDB
can use either of these to access the register.

However, GDB's target descriptions don't really work this way, each
register should appear just once in a target description, mapping the
register name onto the number GDB should use when accessing the
register on the target.  Duplicate register names actually result in
duplicate registers on the GDB side, however, as the registers have
the same name, the user can only access one of these registers.

Currently GDB has a hack in place, specifically for RISC-V, to spot
the duplicate copies of these three registers, and hide them from the
user, ensuring the user only ever sees a single copy of each.

In this commit I propose fixing this issue on the QEMU side, and in
the process, simplify the fpu register handling a little.

I think we should, remove fflags, frm, and fcsr from the two (32-bit
and 64-bit) fpu feature xml files.  These files will only contain the
32 core floating point register f0 to f31.  The fflags, frm, and fcsr
registers will continue to be advertised in the csr feature as they
currently are.

With that change made, I will simplify riscv_gdb_get_fpu and
riscv_gdb_set_fpu, removing the extra handling for the 3 status
registers.

Signed-off-by: Andrew Burgess <aburgess@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <0fbf2a5b12e3210ff3867d5cf7022b3f3462c9c8.1661934573.git.aburgess@redhat.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-27 07:04:38 +10:00
..
aarch64-core.xml target-arm: Add AArch64 gdbstub support 2013-09-10 19:11:28 +01:00
aarch64-fpu.xml target-arm: Support fp registers in gdb stub 2013-12-17 19:42:32 +00:00
arm-core.xml
arm-m-profile-mve.xml target/arm: Advertise MVE to gdb when present 2021-11-02 14:14:55 -04:00
arm-m-profile.xml target/arm: Use correct GDB XML for M-profile cores 2020-05-14 15:03:08 +01:00
arm-neon.xml target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML 2021-09-30 13:42:10 +01:00
arm-vfp-sysregs.xml target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML 2021-09-30 13:42:10 +01:00
arm-vfp.xml target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML 2021-09-30 13:42:10 +01:00
arm-vfp3.xml target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML 2021-09-30 13:42:10 +01:00
avr-cpu.xml target/avr: CPU class: Add GDB support 2020-07-10 17:58:32 +02:00
cf-core.xml
cf-fp.xml
i386-32bit.xml gdbstub: Fix i386/x86_64 machine description and add control registers 2019-02-05 16:50:18 +01:00
i386-64bit.xml gdbstub: Fix i386/x86_64 machine description and add control registers 2019-02-05 16:50:18 +01:00
loongarch-base64.xml target/loongarch: update loongarch-base64.xml 2022-08-05 10:02:40 -07:00
loongarch-fpu.xml target/loongarch: Update loongarch-fpu.xml 2022-08-05 10:02:40 -07:00
m68k-core.xml target/m68k: fix gdb for m68xxx 2020-05-06 09:29:26 +01:00
m68k-fp.xml target-m68k: define 96bit FP registers for gdb on 680x0 2017-06-21 22:11:12 +02:00
power-altivec.xml
power-core.xml gdb-xml: fix hacks in powerpc register numbering 2009-07-12 23:42:05 +02:00
power-fpu.xml gdb-xml: fix hacks in powerpc register numbering 2009-07-12 23:42:05 +02:00
power-spe.xml gdb-xml: fix hacks in powerpc register numbering 2009-07-12 23:42:05 +02:00
power-vsx.xml target-ppc: gdbstub: Add VSX support 2016-01-30 23:37:38 +11:00
power64-core.xml gdb-xml: fix hacks in powerpc register numbering 2009-07-12 23:42:05 +02:00
riscv-32bit-cpu.xml RISC-V: Add 32-bit gdb xml files. 2019-03-19 05:13:24 -07:00
riscv-32bit-fpu.xml target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml 2022-09-27 07:04:38 +10:00
riscv-32bit-virtual.xml target/riscv: Expose "priv" register for GDB for reads 2019-10-28 07:47:29 -07:00
riscv-64bit-cpu.xml RISC-V: Add 64-bit gdb xml files. 2019-03-19 05:13:24 -07:00
riscv-64bit-fpu.xml target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml 2022-09-27 07:04:38 +10:00
riscv-64bit-virtual.xml target/riscv: Expose "priv" register for GDB for reads 2019-10-28 07:47:29 -07:00
rx-core.xml target/rx: CPU definitions 2020-03-19 17:58:05 +01:00
s390-acr.xml s390x/gdb: add the feature xml files for s390x 2014-09-01 09:45:19 +02:00
s390-cr.xml s390x/gdb: support reading/writing of control registers 2015-09-07 16:10:43 +02:00
s390-fpr.xml s390x/gdb: add the feature xml files for s390x 2014-09-01 09:45:19 +02:00
s390-gs.xml s390x/gdb: add gs registers 2017-07-14 12:29:49 +02:00
s390-virt.xml s390x/gdb: expose virtualization specific registers 2015-10-02 13:31:52 +02:00
s390-vx.xml gdb-xml: Include XML for s390 vector registers 2015-05-27 17:52:03 +02:00
s390x-core64.xml s390x/gdb: add the feature xml files for s390x 2014-09-01 09:45:19 +02:00