Bin Meng 722f1352b6 hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card ... This adds the QSPI2 controller to the SoC, and connects an SD card to it. The generation of corresponding device tree source fragment is also added. Specify machine property `msel` to 11 to boot the same upstream U-Boot SPL and payload image for the SiFive HiFive Unleashed board. Note subsequent payload is stored in the SD card image. $ qemu-system-riscv64 -nographic -M sifive_u,msel=11 -smp 5 -m 8G \ -bios u-boot-spl.bin -drive file=sdcard.img,if=sd Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-6-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-03-04 09:43:29 -05:00
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boot.h	riscv: Pass RISCVHartArrayState by pointer	2021-01-16 14:34:46 -08:00
boot_opensbi.h	riscv: Add opensbi firmware dynamic support	2020-07-13 17:25:37 -07:00
microchip_pfsoc.h	hw/riscv: microchip_pfsoc: add QSPI NOR flash	2020-12-17 21:56:43 -08:00
numa.h	hw/riscv: Add helpers for RISC-V multi-socket NUMA machines	2020-08-25 09:11:35 -07:00
opentitan.h	riscv/opentitan: Update the OpenTitan memory layout	2020-12-17 21:56:44 -08:00
riscv_hart.h	Use OBJECT_DECLARE_SIMPLE_TYPE when possible	2020-09-18 14:12:32 -04:00
sifive_cpu.h	riscv: Add a sifive_cpu.h to include both E and U cpu type defines	2019-09-17 08:42:46 -07:00
sifive_e.h	sifive_e: Rename memmap enum constants	2020-09-18 13:49:48 -04:00
sifive_u.h	hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card	2021-03-04 09:43:29 -05:00
spike.h	riscv: spike: Remove target macro conditionals	2020-12-17 21:56:44 -08:00
virt.h	riscv: virt: Remove target macro conditionals	2020-12-17 21:56:44 -08:00