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hw/riscv: microchip_pfsoc: add QSPI NOR flash
Add QSPI NOR flash definition for Microchip PolarFire SoC. Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Message-id: 20201112074950.33283-1-vitaly.wool@konsulko.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -113,6 +113,8 @@ static const struct MemmapEntry {
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[MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
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[MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
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[MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
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[MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 },
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[MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 },
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[MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 },
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[MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
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[MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
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@ -121,6 +123,7 @@ static const struct MemmapEntry {
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[MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
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[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
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[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
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[MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 },
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[MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
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[MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 },
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[MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 },
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@ -185,6 +188,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
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MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
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MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
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MemoryRegion *envm_data = g_new(MemoryRegion, 1);
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MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1);
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char *plic_hart_config;
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size_t plic_hart_config_len;
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NICInfo *nd;
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@ -344,6 +348,14 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
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qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
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serial_hd(4));
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/* SPI */
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create_unimplemented_device("microchip.pfsoc.spi0",
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memmap[MICROCHIP_PFSOC_SPI0].base,
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memmap[MICROCHIP_PFSOC_SPI0].size);
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create_unimplemented_device("microchip.pfsoc.spi1",
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memmap[MICROCHIP_PFSOC_SPI1].base,
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memmap[MICROCHIP_PFSOC_SPI1].size);
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/* I2C1 */
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create_unimplemented_device("microchip.pfsoc.i2c1",
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memmap[MICROCHIP_PFSOC_I2C1].base,
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@ -401,6 +413,15 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
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sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
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memmap[MICROCHIP_PFSOC_IOSCB].base);
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/* QSPI Flash */
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memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
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"microchip.pfsoc.qspi_xip",
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memmap[MICROCHIP_PFSOC_QSPI_XIP].size,
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&error_fatal);
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memory_region_add_subregion(system_memory,
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memmap[MICROCHIP_PFSOC_QSPI_XIP].base,
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qspi_xip_mem);
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}
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static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
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@ -97,6 +97,8 @@ enum {
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MICROCHIP_PFSOC_MMUART2,
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MICROCHIP_PFSOC_MMUART3,
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MICROCHIP_PFSOC_MMUART4,
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MICROCHIP_PFSOC_SPI0,
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MICROCHIP_PFSOC_SPI1,
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MICROCHIP_PFSOC_I2C1,
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MICROCHIP_PFSOC_GEM0,
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MICROCHIP_PFSOC_GEM1,
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@ -105,6 +107,7 @@ enum {
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MICROCHIP_PFSOC_GPIO2,
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MICROCHIP_PFSOC_ENVM_CFG,
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MICROCHIP_PFSOC_ENVM_DATA,
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MICROCHIP_PFSOC_QSPI_XIP,
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MICROCHIP_PFSOC_IOSCB,
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MICROCHIP_PFSOC_DRAM_LO,
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MICROCHIP_PFSOC_DRAM_LO_ALIAS,
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