mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-11-05 20:35:44 +00:00
2507c12ab0
As stated before, devices can be little, big or native endian. The target endianness is not of their concern, so we need to push things down a level. This patch adds a parameter to cpu_register_io_memory that allows a device to choose its endianness. For now, all devices simply choose native endian, because that's the same behavior as before. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
499 lines
12 KiB
C
499 lines
12 KiB
C
/*
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* QEMU Sparc SLAVIO aux io port emulation
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*
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* Copyright (c) 2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "sysemu.h"
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#include "sysbus.h"
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#include "trace.h"
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/*
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* This is the auxio port, chip control and system control part of
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* chip STP2001 (Slave I/O), also produced as NCR89C105. See
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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*
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* This also includes the PMC CPU idle controller.
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*/
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typedef struct MiscState {
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SysBusDevice busdev;
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qemu_irq irq;
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uint32_t dummy;
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uint8_t config;
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uint8_t aux1, aux2;
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uint8_t diag, mctrl;
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uint8_t sysctrl;
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uint16_t leds;
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qemu_irq fdc_tc;
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} MiscState;
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typedef struct APCState {
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SysBusDevice busdev;
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qemu_irq cpu_halt;
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} APCState;
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#define MISC_SIZE 1
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#define SYSCTRL_SIZE 4
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#define AUX1_TC 0x02
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#define AUX2_PWROFF 0x01
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#define AUX2_PWRINTCLR 0x02
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#define AUX2_PWRFAIL 0x20
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#define CFG_PWRINTEN 0x08
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#define SYS_RESET 0x01
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#define SYS_RESETSTAT 0x02
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static void slavio_misc_update_irq(void *opaque)
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{
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MiscState *s = opaque;
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if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
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trace_slavio_misc_update_irq_raise();
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qemu_irq_raise(s->irq);
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} else {
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trace_slavio_misc_update_irq_lower();
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qemu_irq_lower(s->irq);
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}
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}
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static void slavio_misc_reset(DeviceState *d)
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{
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MiscState *s = container_of(d, MiscState, busdev.qdev);
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// Diagnostic and system control registers not cleared in reset
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s->config = s->aux1 = s->aux2 = s->mctrl = 0;
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}
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static void slavio_set_power_fail(void *opaque, int irq, int power_failing)
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{
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MiscState *s = opaque;
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trace_slavio_set_power_fail(power_failing, s->config);
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if (power_failing && (s->config & CFG_PWRINTEN)) {
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s->aux2 |= AUX2_PWRFAIL;
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} else {
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s->aux2 &= ~AUX2_PWRFAIL;
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}
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slavio_misc_update_irq(s);
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}
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static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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MiscState *s = opaque;
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trace_slavio_cfg_mem_writeb(val & 0xff);
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s->config = val & 0xff;
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slavio_misc_update_irq(s);
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}
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static uint32_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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MiscState *s = opaque;
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uint32_t ret = 0;
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ret = s->config;
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trace_slavio_cfg_mem_readb(ret);
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return ret;
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}
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static CPUReadMemoryFunc * const slavio_cfg_mem_read[3] = {
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slavio_cfg_mem_readb,
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NULL,
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NULL,
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};
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static CPUWriteMemoryFunc * const slavio_cfg_mem_write[3] = {
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slavio_cfg_mem_writeb,
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NULL,
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NULL,
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};
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static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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MiscState *s = opaque;
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trace_slavio_diag_mem_writeb(val & 0xff);
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s->diag = val & 0xff;
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}
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static uint32_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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MiscState *s = opaque;
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uint32_t ret = 0;
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ret = s->diag;
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trace_slavio_diag_mem_readb(ret);
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return ret;
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}
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static CPUReadMemoryFunc * const slavio_diag_mem_read[3] = {
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slavio_diag_mem_readb,
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NULL,
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NULL,
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};
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static CPUWriteMemoryFunc * const slavio_diag_mem_write[3] = {
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slavio_diag_mem_writeb,
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NULL,
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NULL,
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};
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static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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MiscState *s = opaque;
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trace_slavio_mdm_mem_writeb(val & 0xff);
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s->mctrl = val & 0xff;
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}
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static uint32_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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MiscState *s = opaque;
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uint32_t ret = 0;
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ret = s->mctrl;
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trace_slavio_mdm_mem_readb(ret);
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return ret;
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}
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static CPUReadMemoryFunc * const slavio_mdm_mem_read[3] = {
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slavio_mdm_mem_readb,
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NULL,
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NULL,
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};
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static CPUWriteMemoryFunc * const slavio_mdm_mem_write[3] = {
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slavio_mdm_mem_writeb,
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NULL,
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NULL,
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};
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static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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MiscState *s = opaque;
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trace_slavio_aux1_mem_writeb(val & 0xff);
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if (val & AUX1_TC) {
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// Send a pulse to floppy terminal count line
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if (s->fdc_tc) {
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qemu_irq_raise(s->fdc_tc);
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qemu_irq_lower(s->fdc_tc);
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}
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val &= ~AUX1_TC;
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}
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s->aux1 = val & 0xff;
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}
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static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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MiscState *s = opaque;
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uint32_t ret = 0;
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ret = s->aux1;
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trace_slavio_aux1_mem_readb(ret);
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return ret;
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}
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static CPUReadMemoryFunc * const slavio_aux1_mem_read[3] = {
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slavio_aux1_mem_readb,
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NULL,
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NULL,
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};
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static CPUWriteMemoryFunc * const slavio_aux1_mem_write[3] = {
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slavio_aux1_mem_writeb,
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NULL,
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NULL,
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};
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static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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MiscState *s = opaque;
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val &= AUX2_PWRINTCLR | AUX2_PWROFF;
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trace_slavio_aux2_mem_writeb(val & 0xff);
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val |= s->aux2 & AUX2_PWRFAIL;
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if (val & AUX2_PWRINTCLR) // Clear Power Fail int
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val &= AUX2_PWROFF;
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s->aux2 = val;
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if (val & AUX2_PWROFF)
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qemu_system_shutdown_request();
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slavio_misc_update_irq(s);
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}
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static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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MiscState *s = opaque;
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uint32_t ret = 0;
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ret = s->aux2;
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trace_slavio_aux2_mem_readb(ret);
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return ret;
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}
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static CPUReadMemoryFunc * const slavio_aux2_mem_read[3] = {
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slavio_aux2_mem_readb,
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NULL,
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NULL,
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};
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static CPUWriteMemoryFunc * const slavio_aux2_mem_write[3] = {
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slavio_aux2_mem_writeb,
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NULL,
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NULL,
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};
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static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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APCState *s = opaque;
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trace_apc_mem_writeb(val & 0xff);
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qemu_irq_raise(s->cpu_halt);
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}
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static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret = 0;
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trace_apc_mem_readb(ret);
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return ret;
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}
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static CPUReadMemoryFunc * const apc_mem_read[3] = {
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apc_mem_readb,
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NULL,
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NULL,
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};
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static CPUWriteMemoryFunc * const apc_mem_write[3] = {
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apc_mem_writeb,
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NULL,
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NULL,
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};
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static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr)
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{
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MiscState *s = opaque;
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uint32_t ret = 0;
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switch (addr) {
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case 0:
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ret = s->sysctrl;
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break;
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default:
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break;
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}
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trace_slavio_sysctrl_mem_readl(ret);
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return ret;
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}
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static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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MiscState *s = opaque;
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trace_slavio_sysctrl_mem_writel(val);
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switch (addr) {
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case 0:
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if (val & SYS_RESET) {
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s->sysctrl = SYS_RESETSTAT;
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qemu_system_reset_request();
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}
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break;
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default:
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break;
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}
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}
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static CPUReadMemoryFunc * const slavio_sysctrl_mem_read[3] = {
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NULL,
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NULL,
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slavio_sysctrl_mem_readl,
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};
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static CPUWriteMemoryFunc * const slavio_sysctrl_mem_write[3] = {
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NULL,
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NULL,
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slavio_sysctrl_mem_writel,
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};
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static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr)
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{
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MiscState *s = opaque;
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uint32_t ret = 0;
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switch (addr) {
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case 0:
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ret = s->leds;
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break;
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default:
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break;
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}
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trace_slavio_led_mem_readw(ret);
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return ret;
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}
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static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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MiscState *s = opaque;
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trace_slavio_led_mem_readw(val & 0xffff);
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switch (addr) {
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case 0:
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s->leds = val;
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break;
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default:
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break;
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}
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}
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static CPUReadMemoryFunc * const slavio_led_mem_read[3] = {
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NULL,
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slavio_led_mem_readw,
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NULL,
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};
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static CPUWriteMemoryFunc * const slavio_led_mem_write[3] = {
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NULL,
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slavio_led_mem_writew,
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NULL,
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};
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static const VMStateDescription vmstate_misc = {
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.name ="slavio_misc",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) {
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VMSTATE_UINT32(dummy, MiscState),
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VMSTATE_UINT8(config, MiscState),
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VMSTATE_UINT8(aux1, MiscState),
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VMSTATE_UINT8(aux2, MiscState),
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VMSTATE_UINT8(diag, MiscState),
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VMSTATE_UINT8(mctrl, MiscState),
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VMSTATE_UINT8(sysctrl, MiscState),
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VMSTATE_END_OF_LIST()
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}
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};
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static int apc_init1(SysBusDevice *dev)
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{
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APCState *s = FROM_SYSBUS(APCState, dev);
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int io;
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sysbus_init_irq(dev, &s->cpu_halt);
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/* Power management (APC) XXX: not a Slavio device */
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io = cpu_register_io_memory(apc_mem_read, apc_mem_write, s,
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DEVICE_NATIVE_ENDIAN);
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sysbus_init_mmio(dev, MISC_SIZE, io);
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return 0;
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}
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static int slavio_misc_init1(SysBusDevice *dev)
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{
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MiscState *s = FROM_SYSBUS(MiscState, dev);
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int io;
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sysbus_init_irq(dev, &s->irq);
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sysbus_init_irq(dev, &s->fdc_tc);
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/* 8 bit registers */
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/* Slavio control */
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io = cpu_register_io_memory(slavio_cfg_mem_read,
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slavio_cfg_mem_write, s,
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DEVICE_NATIVE_ENDIAN);
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sysbus_init_mmio(dev, MISC_SIZE, io);
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/* Diagnostics */
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io = cpu_register_io_memory(slavio_diag_mem_read,
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slavio_diag_mem_write, s,
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DEVICE_NATIVE_ENDIAN);
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sysbus_init_mmio(dev, MISC_SIZE, io);
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/* Modem control */
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io = cpu_register_io_memory(slavio_mdm_mem_read,
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slavio_mdm_mem_write, s,
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DEVICE_NATIVE_ENDIAN);
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sysbus_init_mmio(dev, MISC_SIZE, io);
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/* 16 bit registers */
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/* ss600mp diag LEDs */
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io = cpu_register_io_memory(slavio_led_mem_read,
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slavio_led_mem_write, s,
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DEVICE_NATIVE_ENDIAN);
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sysbus_init_mmio(dev, MISC_SIZE, io);
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/* 32 bit registers */
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/* System control */
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io = cpu_register_io_memory(slavio_sysctrl_mem_read,
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slavio_sysctrl_mem_write, s,
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DEVICE_NATIVE_ENDIAN);
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sysbus_init_mmio(dev, SYSCTRL_SIZE, io);
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/* AUX 1 (Misc System Functions) */
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io = cpu_register_io_memory(slavio_aux1_mem_read,
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slavio_aux1_mem_write, s,
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DEVICE_NATIVE_ENDIAN);
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sysbus_init_mmio(dev, MISC_SIZE, io);
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/* AUX 2 (Software Powerdown Control) */
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io = cpu_register_io_memory(slavio_aux2_mem_read,
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slavio_aux2_mem_write, s,
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DEVICE_NATIVE_ENDIAN);
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sysbus_init_mmio(dev, MISC_SIZE, io);
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qdev_init_gpio_in(&dev->qdev, slavio_set_power_fail, 1);
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return 0;
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}
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static SysBusDeviceInfo slavio_misc_info = {
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.init = slavio_misc_init1,
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.qdev.name = "slavio_misc",
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.qdev.size = sizeof(MiscState),
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.qdev.vmsd = &vmstate_misc,
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.qdev.reset = slavio_misc_reset,
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};
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static SysBusDeviceInfo apc_info = {
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.init = apc_init1,
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.qdev.name = "apc",
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.qdev.size = sizeof(MiscState),
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};
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static void slavio_misc_register_devices(void)
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{
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sysbus_register_withprop(&slavio_misc_info);
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sysbus_register_withprop(&apc_info);
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}
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device_init(slavio_misc_register_devices)
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