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Add endianness as io mem parameter

Browse source 
As stated before, devices can be little, big or native endian. The
target endianness is not of their concern, so we need to push things
down a level.

This patch adds a parameter to cpu_register_io_memory that allows a
device to choose its endianness. For now, all devices simply choose
native endian, because that's the same behavior as before.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Alexander Graf 2010-12-08 12:05:37 +01:00 committed by Blue Swirl
parent dd310534e3
commit 2507c12ab0
154 changed files with 446 additions and 262 deletions
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21
exec.c
View file

@ -3331,7 +3331,8 @@ static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
mmio = qemu_mallocz(sizeof(subpage_t));
mmio->base = base;
subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio);
subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio,
DEVICE_NATIVE_ENDIAN);
#if defined(DEBUG_SUBPAGE)
printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__,
mmio, base, TARGET_PAGE_SIZE, subpage_memory);
@ -3468,7 +3469,6 @@ static int cpu_register_io_memory_fixed(int io_index,
void *opaque, enum device_endian endian)
{
int i;
int endian = DEVICE_NATIVE_ENDIAN;
if (io_index <= 0) {
io_index = get_free_io_mem_idx();
@ -3513,7 +3513,7 @@ int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
CPUWriteMemoryFunc * const *mem_write,
void *opaque, enum device_endian endian)
{
return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque);
return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque, endian);
}
void cpu_unregister_io_memory(int io_table_address)
@ -3535,14 +3535,21 @@ static void io_mem_init(void)
{
int i;
cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read, unassigned_mem_write, NULL);
cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read, unassigned_mem_write, NULL);
cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read, notdirty_mem_write, NULL);
cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read,
unassigned_mem_write, NULL,
DEVICE_NATIVE_ENDIAN);
cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read,
unassigned_mem_write, NULL,
DEVICE_NATIVE_ENDIAN);
cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read,
notdirty_mem_write, NULL,
DEVICE_NATIVE_ENDIAN);
for (i=0; i<5; i++)
io_mem_used[i] = 1;
io_mem_watch = cpu_register_io_memory(watch_mem_read,
watch_mem_write, NULL);
watch_mem_write, NULL,
DEVICE_NATIVE_ENDIAN);
}
#endif /* !defined(CONFIG_USER_ONLY) */

6
hw/apb_pci.c
View file

@ -410,7 +410,8 @@ static int pci_pbm_init_device(SysBusDevice *dev)
/* apb_config */
apb_config = cpu_register_io_memory(apb_config_read,
apb_config_write, s);
apb_config_write, s,
DEVICE_NATIVE_ENDIAN);
/* at region 0 */
sysbus_init_mmio(dev, 0x10000ULL, apb_config);
@ -424,7 +425,8 @@ static int pci_pbm_init_device(SysBusDevice *dev)
/* pci_ioport */
pci_ioport = cpu_register_io_memory(pci_apb_ioread,
pci_apb_iowrite, s);
pci_apb_iowrite, s,
DEVICE_NATIVE_ENDIAN);
/* at region 2 */
sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);

3
hw/apic.c
View file

@ -980,7 +980,8 @@ static int apic_init1(SysBusDevice *dev)
return -1;
}
apic_io_memory = cpu_register_io_memory(apic_mem_read,
apic_mem_write, NULL);
apic_mem_write, NULL,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MSI_ADDR_SIZE, apic_io_memory);
s->timer = qemu_new_timer(vm_clock, apic_timer, s);

3
hw/arm_gic.c
View file

@ -742,7 +742,8 @@ static void gic_init(gic_state *s)
sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
}
s->iomemtype = cpu_register_io_memory(gic_dist_readfn,
gic_dist_writefn, s);
gic_dist_writefn, s,
DEVICE_NATIVE_ENDIAN);
gic_reset(s);
register_savevm(NULL, "arm_gic", -1, 1, gic_save, gic_load, s);
}

3
hw/arm_sysctl.c
View file

@ -208,7 +208,8 @@ static int arm_sysctl_init1(SysBusDevice *dev)
int iomemtype;
iomemtype = cpu_register_io_memory(arm_sysctl_readfn,
arm_sysctl_writefn, s);
arm_sysctl_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
/* ??? Save/restore. */
return 0;

5
hw/arm_timer.c
View file

@ -269,7 +269,7 @@ static int sp804_init(SysBusDevice *dev)
s->timer[0]->irq = qi[0];
s->timer[1]->irq = qi[1];
iomemtype = cpu_register_io_memory(sp804_readfn,
sp804_writefn, s);
sp804_writefn, s, DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
register_savevm(&dev->qdev, "sp804", -1, 1, sp804_save, sp804_load, s);
return 0;
@ -340,7 +340,8 @@ static int icp_pit_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->timer[2]->irq);
iomemtype = cpu_register_io_memory(icp_pit_readfn,
icp_pit_writefn, s);
icp_pit_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
/* This device has no state to save/restore. The component timers will
save themselves. */

2
hw/armv7m.c
View file

@ -130,7 +130,7 @@ static int bitband_init(SysBusDevice *dev)
int iomemtype;
iomemtype = cpu_register_io_memory(bitband_readfn, bitband_writefn,
&s->base);
&s->base, DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x02000000, iomemtype);
return 0;
}

6
hw/axis_dev88.c
View file

@ -280,11 +280,13 @@ void axisdev88_init (ram_addr_t ram_size,
/* Attach a NAND flash to CS1. */
nand_state.nand = nand_init(NAND_MFR_STMICRO, 0x39);
nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state);
nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs);
gpio_state.nand = &nand_state;
gpio_regs = cpu_register_io_memory(gpio_read, gpio_write, &gpio_state);
gpio_regs = cpu_register_io_memory(gpio_read, gpio_write, &gpio_state,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs);

15
hw/bonito.c
View file

@ -698,7 +698,8 @@ static int bonito_initfn(PCIDevice *dev)
pci_config_set_revision(dev->config, 0x01);
/* set the north bridge register mapping */
s->bonito_reg_handle = cpu_register_io_memory(bonito_read, bonito_write, s);
s->bonito_reg_handle = cpu_register_io_memory(bonito_read, bonito_write, s,
DEVICE_NATIVE_ENDIAN);
s->bonito_reg_start = BONITO_INTERNAL_REG_BASE;
s->bonito_reg_length = BONITO_INTERNAL_REG_SIZE;
cpu_register_physical_memory(s->bonito_reg_start, s->bonito_reg_length,
@ -706,7 +707,8 @@ static int bonito_initfn(PCIDevice *dev)
/* set the north bridge pci configure mapping */
s->bonito_pciconf_handle = cpu_register_io_memory(bonito_pciconf_read,
bonito_pciconf_write, s);
bonito_pciconf_write, s,
DEVICE_NATIVE_ENDIAN);
s->bonito_pciconf_start = BONITO_PCICONFIG_BASE;
s->bonito_pciconf_length = BONITO_PCICONFIG_SIZE;
cpu_register_physical_memory(s->bonito_pciconf_start, s->bonito_pciconf_length,
@ -714,21 +716,24 @@ static int bonito_initfn(PCIDevice *dev)
/* set the south bridge pci configure mapping */
s->bonito_spciconf_handle = cpu_register_io_memory(bonito_spciconf_read,
bonito_spciconf_write, s);
bonito_spciconf_write, s,
DEVICE_NATIVE_ENDIAN);
s->bonito_spciconf_start = BONITO_SPCICONFIG_BASE;
s->bonito_spciconf_length = BONITO_SPCICONFIG_SIZE;
cpu_register_physical_memory(s->bonito_spciconf_start, s->bonito_spciconf_length,
s->bonito_spciconf_handle);
s->bonito_ldma_handle = cpu_register_io_memory(bonito_ldma_read,
bonito_ldma_write, s);
bonito_ldma_write, s,
DEVICE_NATIVE_ENDIAN);
s->bonito_ldma_start = 0xbfe00200;
s->bonito_ldma_length = 0x100;
cpu_register_physical_memory(s->bonito_ldma_start, s->bonito_ldma_length,
s->bonito_ldma_handle);
s->bonito_cop_handle = cpu_register_io_memory(bonito_cop_read,
bonito_cop_write, s);
bonito_cop_write, s,
DEVICE_NATIVE_ENDIAN);
s->bonito_cop_start = 0xbfe00300;
s->bonito_cop_length = 0x100;
cpu_register_physical_memory(s->bonito_cop_start, s->bonito_cop_length,

12
hw/cirrus_vga.c
View file

@ -3076,23 +3076,27 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
register_ioport_read(0x3da, 1, 1, cirrus_vga_ioport_read, s);
s->vga.vga_io_memory = cpu_register_io_memory(cirrus_vga_mem_read,
cirrus_vga_mem_write, s);
cirrus_vga_mem_write, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
s->vga.vga_io_memory);
qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
/* I/O handler for LFB */
s->cirrus_linear_io_addr =
cpu_register_io_memory(cirrus_linear_read, cirrus_linear_write, s);
cpu_register_io_memory(cirrus_linear_read, cirrus_linear_write, s,
DEVICE_NATIVE_ENDIAN);
/* I/O handler for LFB */
s->cirrus_linear_bitblt_io_addr =
cpu_register_io_memory(cirrus_linear_bitblt_read,
cirrus_linear_bitblt_write, s);
cirrus_linear_bitblt_write, s,
DEVICE_NATIVE_ENDIAN);
/* I/O handler for memory-mapped I/O */
s->cirrus_mmio_io_addr =
cpu_register_io_memory(cirrus_mmio_read, cirrus_mmio_write, s);
cpu_register_io_memory(cirrus_mmio_read, cirrus_mmio_write, s,
DEVICE_NATIVE_ENDIAN);
s->real_vram_size =
(s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;

3
hw/cs4231.c
View file

@ -148,7 +148,8 @@ static int cs4231_init1(SysBusDevice *dev)
int io;
CSState *s = FROM_SYSBUS(CSState, dev);
io = cpu_register_io_memory(cs_mem_read, cs_mem_write, s);
io = cpu_register_io_memory(cs_mem_read, cs_mem_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, CS_SIZE, io);
sysbus_init_irq(dev, &s->irq);

3
hw/cuda.c
View file

@ -762,7 +762,8 @@ void cuda_init (int *cuda_mem_index, qemu_irq irq)
s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET;
s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s);
*cuda_mem_index = cpu_register_io_memory(cuda_read, cuda_write, s);
*cuda_mem_index = cpu_register_io_memory(cuda_read, cuda_write, s,
DEVICE_NATIVE_ENDIAN);
register_savevm(NULL, "cuda", -1, 1, cuda_save, cuda_load, s);
qemu_register_reset(cuda_reset, s);
}

3
hw/dp8393x.c
View file

@ -908,6 +908,7 @@ void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
qemu_register_reset(nic_reset, s);
nic_reset(s);
s->mmio_index = cpu_register_io_memory(dp8393x_read, dp8393x_write, s);
s->mmio_index = cpu_register_io_memory(dp8393x_read, dp8393x_write, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x40 << it_shift, s->mmio_index);
}

6
hw/ds1225y.c
View file

@ -171,10 +171,12 @@ void *ds1225y_init(target_phys_addr_t mem_base, const char *filename)
}
/* Read/write memory */
mem_indexRW = cpu_register_io_memory(nvram_read, nvram_write, s);
mem_indexRW = cpu_register_io_memory(nvram_read, nvram_write, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(mem_base, s->chip_size, mem_indexRW);
/* Read/write protected memory */
mem_indexRP = cpu_register_io_memory(nvram_read, nvram_write_protected, s);
mem_indexRP = cpu_register_io_memory(nvram_read, nvram_write_protected, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(mem_base + s->chip_size, s->chip_size, mem_indexRP);
return s;
}

2
hw/e1000.c
View file

@ -1131,7 +1131,7 @@ static int pci_e1000_init(PCIDevice *pci_dev)
pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0
d->mmio_index = cpu_register_io_memory(e1000_mmio_read,
e1000_mmio_write, d);
e1000_mmio_write, d, DEVICE_NATIVE_ENDIAN);
pci_register_bar(&d->dev, 0, PNPMMIO_SIZE,
PCI_BASE_ADDRESS_SPACE_MEMORY, e1000_mmio_map);

6
hw/eccmemctl.c
View file

@ -297,12 +297,14 @@ static int ecc_init1(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
s->regs[0] = s->version;
ecc_io_memory = cpu_register_io_memory(ecc_mem_read, ecc_mem_write, s);
ecc_io_memory = cpu_register_io_memory(ecc_mem_read, ecc_mem_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, ECC_SIZE, ecc_io_memory);
if (s->version == ECC_MCC) { // SS-600MP only
ecc_io_memory = cpu_register_io_memory(ecc_diag_mem_read,
ecc_diag_mem_write, s);
ecc_diag_mem_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, ECC_DIAG_SIZE, ecc_io_memory);
}

3
hw/eepro100.c
View file

@ -1878,7 +1878,8 @@ static int e100_nic_init(PCIDevice *pci_dev)
/* Handler for memory-mapped I/O */
s->mmio_index =
cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s);
cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s,
DEVICE_NATIVE_ENDIAN);
pci_register_bar(&s->dev, 0, PCI_MEM_SIZE,
PCI_BASE_ADDRESS_SPACE_MEMORY |

3
hw/empty_slot.c
View file

@ -73,7 +73,8 @@ static int empty_slot_init1(SysBusDevice *dev)
ram_addr_t empty_slot_offset;
empty_slot_offset = cpu_register_io_memory(empty_slot_read,
empty_slot_write, s);
empty_slot_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, s->size, empty_slot_offset | IO_MEM_RAM);
return 0;
}

3
hw/escc.c
View file

@ -914,7 +914,8 @@ static int escc_init1(SysBusDevice *dev)
s->chn[0].otherchn = &s->chn[1];
s->chn[1].otherchn = &s->chn[0];
io = cpu_register_io_memory(escc_mem_read, escc_mem_write, s);
io = cpu_register_io_memory(escc_mem_read, escc_mem_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, ESCC_SIZE << s->it_shift, io);
s->mmio_index = io;

3
hw/esp.c
View file

@ -722,7 +722,8 @@ static int esp_init1(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
assert(s->it_shift != -1);
esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s);
esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory);
qdev_init_gpio_in(&dev->qdev, esp_gpio_demux, 2);

2
hw/etraxfs_dma.c
View file

@ -750,7 +750,7 @@ void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels)
ctrl->nr_channels = nr_channels;
ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels);
ctrl->map = cpu_register_io_memory(dma_read, dma_write, ctrl);
ctrl->map = cpu_register_io_memory(dma_read, dma_write, ctrl, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, nr_channels * 0x2000, ctrl->map);
return ctrl;
}

3
hw/etraxfs_eth.c
View file

@ -598,7 +598,8 @@ void *etraxfs_eth_init(NICInfo *nd, target_phys_addr_t base, int phyaddr)
tdk_init(&eth->phy);
mdio_attach(&eth->mdio_bus, &eth->phy, eth->phyaddr);
eth->ethregs = cpu_register_io_memory(eth_read, eth_write, eth);
eth->ethregs = cpu_register_io_memory(eth_read, eth_write, eth,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory (base, 0x5c, eth->ethregs);
memcpy(eth->conf.macaddr.a, nd->macaddr, sizeof(nd->macaddr));

3
hw/etraxfs_pic.c
View file

@ -145,7 +145,8 @@ static int etraxfs_pic_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->parent_irq);
sysbus_init_irq(dev, &s->parent_nmi);
intr_vect_regs = cpu_register_io_memory(pic_read, pic_write, s);
intr_vect_regs = cpu_register_io_memory(pic_read, pic_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, R_MAX * 4, intr_vect_regs);
return 0;
}

3
hw/etraxfs_ser.c
View file

@ -200,7 +200,8 @@ static int etraxfs_ser_init(SysBusDevice *dev)
s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);
sysbus_init_irq(dev, &s->irq);
ser_regs = cpu_register_io_memory(ser_read, ser_write, s);
ser_regs = cpu_register_io_memory(ser_read, ser_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, R_MAX * 4, ser_regs);
s->chr = qdev_init_chardev(&dev->qdev);
if (s->chr)

3
hw/etraxfs_timer.c
View file

@ -323,7 +323,8 @@ static int etraxfs_timer_init(SysBusDevice *dev)
sysbus_init_irq(dev, &t->irq);
sysbus_init_irq(dev, &t->nmi);
timer_regs = cpu_register_io_memory(timer_read, timer_write, t);
timer_regs = cpu_register_io_memory(timer_read, timer_write, t,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x5c, timer_regs);
qemu_register_reset(etraxfs_timer_reset, t);

6
hw/fdc.c
View file

@ -1999,7 +1999,8 @@ static int sysbus_fdc_init1(SysBusDevice *dev)
int io;
int ret;
io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl);
io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x08, io);
sysbus_init_irq(dev, &fdctrl->irq);
qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
@ -2017,7 +2018,8 @@ static int sun4m_fdc_init1(SysBusDevice *dev)
int io;
io = cpu_register_io_memory(fdctrl_mem_read_strict,
fdctrl_mem_write_strict, fdctrl);
fdctrl_mem_write_strict, fdctrl,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x08, io);
sysbus_init_irq(dev, &fdctrl->irq);
qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);

6
hw/fw_cfg.c
View file

@ -360,11 +360,13 @@ static int fw_cfg_init1(SysBusDevice *dev)
int io_ctl_memory, io_data_memory;
io_ctl_memory = cpu_register_io_memory(fw_cfg_ctl_mem_read,
fw_cfg_ctl_mem_write, s);
fw_cfg_ctl_mem_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, FW_CFG_SIZE, io_ctl_memory);
io_data_memory = cpu_register_io_memory(fw_cfg_data_mem_read,
fw_cfg_data_mem_write, s);
fw_cfg_data_mem_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, FW_CFG_SIZE, io_data_memory);
if (s->ctl_iobase) {

3
hw/g364fb.c
View file

@ -607,7 +607,8 @@ int g364fb_mm_init(target_phys_addr_t vram_base,
cpu_register_physical_memory(vram_base, s->vram_size, s->vram_offset);
io_ctrl = cpu_register_io_memory(g364fb_ctrl_read, g364fb_ctrl_write, s);
io_ctrl = cpu_register_io_memory(g364fb_ctrl_read, g364fb_ctrl_write, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(ctrl_base, 0x200000, io_ctrl);
return 0;

3
hw/gt64xxx.c
View file

@ -1116,7 +1116,8 @@ PCIBus *pci_gt64120_init(qemu_irq *pic)
s->pci->bus = pci_register_bus(NULL, "pci",
pci_gt64120_set_irq, pci_gt64120_map_irq,
pic, PCI_DEVFN(18, 0), 4);
s->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, s);
s->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, s,
DEVICE_NATIVE_ENDIAN);
d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice),
0, NULL, NULL);

3
hw/heathrow_pic.c
View file

@ -222,7 +222,8 @@ qemu_irq *heathrow_pic_init(int *pmem_index,
s = qemu_mallocz(sizeof(HeathrowPICS));
/* only 1 CPU */
s->irqs = irqs[0];
*pmem_index = cpu_register_io_memory(pic_read, pic_write, s);
*pmem_index = cpu_register_io_memory(pic_read, pic_write, s,
DEVICE_NATIVE_ENDIAN);
register_savevm(NULL, "heathrow_pic", -1, 1, heathrow_pic_save,
heathrow_pic_load, s);

3
hw/hpet.c
View file

@ -720,7 +720,8 @@ static int hpet_init(SysBusDevice *dev)
/* HPET Area */
iomemtype = cpu_register_io_memory(hpet_ram_read,
hpet_ram_write, s);
hpet_ram_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x400, iomemtype);
return 0;
}

3
hw/ide/macio.c
View file

@ -320,7 +320,8 @@ int pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d);
pmac_ide_memory = cpu_register_io_memory(pmac_ide_read,
pmac_ide_write, d);
pmac_ide_write, d,
DEVICE_NATIVE_ENDIAN);
vmstate_register(NULL, 0, &vmstate_pmac, d);
qemu_register_reset(pmac_ide_reset, d);

6
hw/ide/mmio.c
View file

@ -129,8 +129,10 @@ void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
s->shift = shift;
mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s);
mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s);
mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s,
DEVICE_NATIVE_ENDIAN);
mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(membase, 16 << shift, mem1);
cpu_register_physical_memory(membase2, 2 << shift, mem2);
vmstate_register(NULL, 0, &vmstate_ide_mmio, s);

9
hw/integratorcp.c
View file

@ -256,7 +256,8 @@ static int integratorcm_init(SysBusDevice *dev)
s->flash_offset = qemu_ram_alloc(NULL, "integrator.flash", 0x100000);
iomemtype = cpu_register_io_memory(integratorcm_readfn,
integratorcm_writefn, s);
integratorcm_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x00800000, iomemtype);
integratorcm_do_remap(s, 1);
/* ??? Save/restore. */
@ -382,7 +383,8 @@ static int icp_pic_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->parent_irq);
sysbus_init_irq(dev, &s->parent_fiq);
iomemtype = cpu_register_io_memory(icp_pic_readfn,
icp_pic_writefn, s);
icp_pic_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x00800000, iomemtype);
return 0;
}
@ -435,7 +437,8 @@ static void icp_control_init(uint32_t base)
int iomemtype;
iomemtype = cpu_register_io_memory(icp_control_readfn,
icp_control_writefn, NULL);
icp_control_writefn, NULL,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00800000, iomemtype);
/* ??? Save/restore. */
}

3
hw/intel-hda.c
View file

@ -1156,7 +1156,8 @@ static int intel_hda_init(PCIDevice *pci)
conf[0x40] = 0x01;
d->mmio_addr = cpu_register_io_memory(intel_hda_mmio_read,
intel_hda_mmio_write, d);
intel_hda_mmio_write, d,
DEVICE_NATIVE_ENDIAN);
pci_register_bar(&d->pci, 0, 0x4000, PCI_BASE_ADDRESS_SPACE_MEMORY,
intel_hda_map);
if (d->msi) {

3
hw/ioapic.c
View file

@ -242,7 +242,8 @@ static int ioapic_init1(SysBusDevice *dev)
int io_memory;
io_memory = cpu_register_io_memory(ioapic_mem_read,
ioapic_mem_write, s);
ioapic_mem_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, io_memory);
qdev_init_gpio_in(&dev->qdev, ioapic_set_irq, IOAPIC_NUM_PINS);

6
hw/isa_mmio.c
View file

@ -131,11 +131,13 @@ void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be)
if (be) {
isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read_be,
isa_mmio_write_be,
NULL);
NULL,
DEVICE_NATIVE_ENDIAN);
} else {
isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read_le,
isa_mmio_write_le,
NULL);
NULL,
DEVICE_NATIVE_ENDIAN);
}
}
cpu_register_physical_memory(base, size, isa_mmio_iomemtype);

2
hw/ivshmem.c
View file

@ -720,7 +720,7 @@ static int pci_ivshmem_init(PCIDevice *dev)
s->shm_fd = 0;
s->ivshmem_mmio_io_addr = cpu_register_io_memory(ivshmem_mmio_read,
ivshmem_mmio_write, s);
ivshmem_mmio_write, s, DEVICE_NATIVE_ENDIAN);
/* region for registers*/
pci_register_bar(&s->dev, 0, IVSHMEM_REG_BAR_SIZE,
PCI_BASE_ADDRESS_SPACE_MEMORY, ivshmem_mmio_map);

3
hw/jazz_led.c
View file

@ -316,7 +316,8 @@ void jazz_led_init(target_phys_addr_t base)
s->state = REDRAW_SEGMENTS | REDRAW_BACKGROUND;
io = cpu_register_io_memory(led_read, led_write, s);
io = cpu_register_io_memory(led_read, led_write, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 1, io);
s->ds = graphic_console_init(jazz_led_update_display,

3
hw/lan9118.c
View file

@ -1124,7 +1124,8 @@ static int lan9118_init1(SysBusDevice *dev)
int i;
s->mmio_index = cpu_register_io_memory(lan9118_readfn,
lan9118_writefn, s);
lan9118_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x100, s->mmio_index);
sysbus_init_irq(dev, &s->irq);
qemu_macaddr_default_if_unset(&s->conf.macaddr);

3
hw/lance.c
View file

@ -118,7 +118,8 @@ static int lance_init(SysBusDevice *dev)
PCNetState *s = &d->state;
s->mmio_index =
cpu_register_io_memory(lance_mem_read, lance_mem_write, d);
cpu_register_io_memory(lance_mem_read, lance_mem_write, d,
DEVICE_NATIVE_ENDIAN);
qdev_init_gpio_in(&dev->qdev, parent_lance_reset, 1);

6
hw/lsi53c895a.c
View file

@ -2173,9 +2173,11 @@ static int lsi_scsi_init(PCIDevice *dev)
pci_conf[PCI_INTERRUPT_PIN] = 0x01;
s->mmio_io_addr = cpu_register_io_memory(lsi_mmio_readfn,
lsi_mmio_writefn, s);
lsi_mmio_writefn, s,
DEVICE_NATIVE_ENDIAN);
s->ram_io_addr = cpu_register_io_memory(lsi_ram_readfn,
lsi_ram_writefn, s);
lsi_ram_writefn, s,
DEVICE_NATIVE_ENDIAN);
pci_register_bar(&s->dev, 0, 256,
PCI_BASE_ADDRESS_SPACE_IO, lsi_io_mapfunc);

3
hw/m48t59.c
View file

@ -716,7 +716,8 @@ static int m48t59_init1(SysBusDevice *dev)
sysbus_init_irq(dev, &s->IRQ);
mem_index = cpu_register_io_memory(nvram_read, nvram_write, s);
mem_index = cpu_register_io_memory(nvram_read, nvram_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, s->size, mem_index);
m48t59_init_common(s);

3
hw/mac_dbdma.c
View file

@ -844,7 +844,8 @@ void* DBDMA_init (int *dbdma_mem_index)
s = qemu_mallocz(sizeof(DBDMA_channel) * DBDMA_CHANNELS);
*dbdma_mem_index = cpu_register_io_memory(dbdma_read, dbdma_write, s);
*dbdma_mem_index = cpu_register_io_memory(dbdma_read, dbdma_write, s,
DEVICE_NATIVE_ENDIAN);
register_savevm(NULL, "dbdma", -1, 1, dbdma_save, dbdma_load, s);
qemu_register_reset(dbdma_reset, s);

3
hw/mac_nvram.c
View file

@ -138,7 +138,8 @@ MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size,
s->size = size;
s->it_shift = it_shift;
s->mem_index = cpu_register_io_memory(nvram_read, nvram_write, s);
s->mem_index = cpu_register_io_memory(nvram_read, nvram_write, s,
DEVICE_NATIVE_ENDIAN);
*mem_index = s->mem_index;
register_savevm(NULL, "macio_nvram", -1, 1, macio_nvram_save,
macio_nvram_load, s);

3
hw/marvell_88w8618_audio.c
View file

@ -249,7 +249,8 @@ static int mv88w8618_audio_init(SysBusDevice *dev)
wm8750_data_req_set(s->wm, mv88w8618_audio_callback, s);
iomemtype = cpu_register_io_memory(mv88w8618_audio_readfn,
mv88w8618_audio_writefn, s);
mv88w8618_audio_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MP_AUDIO_SIZE, iomemtype);
return 0;

3
hw/mcf5206.c
View file

@ -525,7 +525,8 @@ qemu_irq *mcf5206_init(uint32_t base, CPUState *env)
s = (m5206_mbar_state *)qemu_mallocz(sizeof(m5206_mbar_state));
iomemtype = cpu_register_io_memory(m5206_mbar_readfn,
m5206_mbar_writefn, s);
m5206_mbar_writefn, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00001000, iomemtype);
pic = qemu_allocate_irqs(m5206_mbar_set_irq, s, 14);

6
hw/mcf5208.c
View file

@ -179,7 +179,8 @@ static void mcf5208_sys_init(qemu_irq *pic)
int i;
iomemtype = cpu_register_io_memory(m5208_sys_readfn,
m5208_sys_writefn, NULL);
m5208_sys_writefn, NULL,
DEVICE_NATIVE_ENDIAN);
/* SDRAMC. */
cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype);
/* Timers. */
@ -188,7 +189,8 @@ static void mcf5208_sys_init(qemu_irq *pic)
bh = qemu_bh_new(m5208_timer_trigger, s);
s->timer = ptimer_init(bh);
iomemtype = cpu_register_io_memory(m5208_timer_readfn,
m5208_timer_writefn, s);
m5208_timer_writefn, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0xfc080000 + 0x4000 * i, 0x00004000,
iomemtype);
s->irq = pic[4 + i];

3
hw/mcf_fec.c
View file

@ -467,7 +467,8 @@ void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq)
s = (mcf_fec_state *)qemu_mallocz(sizeof(mcf_fec_state));
s->irq = irq;
s->mmio_index = cpu_register_io_memory(mcf_fec_readfn,
mcf_fec_writefn, s);
mcf_fec_writefn, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x400, s->mmio_index);
memcpy(s->conf.macaddr.a, nd->macaddr, sizeof(nd->macaddr));

3
hw/mcf_intc.c
View file

@ -149,7 +149,8 @@ qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env)
mcf_intc_reset(s);
iomemtype = cpu_register_io_memory(mcf_intc_readfn,
mcf_intc_writefn, s);
mcf_intc_writefn, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x100, iomemtype);
return qemu_allocate_irqs(mcf_intc_set_irq, s, 64);

3
hw/mcf_uart.c
View file

@ -304,6 +304,7 @@ void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
s = mcf_uart_init(irq, chr);
iomemtype = cpu_register_io_memory(mcf_uart_readfn,
mcf_uart_writefn, s);
mcf_uart_writefn, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x40, iomemtype);
}

6
hw/mips_jazz.c
View file

@ -191,7 +191,8 @@ void mips_jazz_init (ram_addr_t ram_size,
/* Chipset */
rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);
s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL);
s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
/* ISA devices */
@ -259,7 +260,8 @@ void mips_jazz_init (ram_addr_t ram_size,
/* Real time clock */
rtc_init(1980, NULL);
s_rtc = cpu_register_io_memory(rtc_read, rtc_write, NULL);
s_rtc = cpu_register_io_memory(rtc_read, rtc_write, NULL,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);
/* Keyboard (i8042) */

3
hw/mips_malta.c
View file

@ -436,7 +436,8 @@ static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, qemu_irq uart_ir
s = (MaltaFPGAState *)qemu_mallocz(sizeof(MaltaFPGAState));
malta = cpu_register_io_memory(malta_fpga_read,
malta_fpga_write, s);
malta_fpga_write, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x900, malta);
/* 0xa00 is less than a page, so will still get the right offsets. */

3
hw/mips_r4k.c
View file

@ -204,7 +204,8 @@ void mips_r4k_init (ram_addr_t ram_size,
if (!mips_qemu_iomemtype) {
mips_qemu_iomemtype = cpu_register_io_memory(mips_qemu_read,
mips_qemu_write, NULL);
mips_qemu_write, NULL,
DEVICE_NATIVE_ENDIAN);
}
cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype);

3
hw/mpcore.c
View file

@ -276,7 +276,8 @@ static int mpcore_priv_init(SysBusDevice *dev)
gic_init(&s->gic, s->num_cpu);
s->iomemtype = cpu_register_io_memory(mpcore_priv_readfn,
mpcore_priv_writefn, s);
mpcore_priv_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio_cb(dev, 0x2000, mpcore_priv_map);
for (i = 0; i < s->num_cpu * 2; i++) {
mpcore_timer_init(s, &s->timer[i], i);

3
hw/msix.c
View file

@ -254,7 +254,8 @@ int msix_init(struct PCIDevice *dev, unsigned short nentries,
msix_mask_all(dev, nentries);
dev->msix_mmio_index = cpu_register_io_memory(msix_mmio_read,
msix_mmio_write, dev);
msix_mmio_write, dev,
DEVICE_NATIVE_ENDIAN);
if (dev->msix_mmio_index == -1) {
ret = -EBUSY;
goto err_index;

2
hw/mst_fpga.c
View file

@ -232,7 +232,7 @@ qemu_irq *mst_irq_init(PXA2xxState *cpu, uint32_t base, int irq)
s->pins = qi;
iomemtype = cpu_register_io_memory(mst_fpga_readfn,
mst_fpga_writefn, s);
mst_fpga_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00100000, iomemtype);
register_savevm(NULL, "mainstone_fpga", 0, 0, mst_fpga_save,
mst_fpga_load, s);

24
hw/musicpal.c
View file

@ -388,7 +388,8 @@ static int mv88w8618_eth_init(SysBusDevice *dev)
s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf,
dev->qdev.info->name, dev->qdev.id, s);
s->mmio_index = cpu_register_io_memory(mv88w8618_eth_readfn,
mv88w8618_eth_writefn, s);
mv88w8618_eth_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MP_ETH_SIZE, s->mmio_index);
return 0;
}
@ -600,7 +601,8 @@ static int musicpal_lcd_init(SysBusDevice *dev)
s->brightness = 7;
iomemtype = cpu_register_io_memory(musicpal_lcd_readfn,
musicpal_lcd_writefn, s);
musicpal_lcd_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype);
s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
@ -725,7 +727,8 @@ static int mv88w8618_pic_init(SysBusDevice *dev)
qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
sysbus_init_irq(dev, &s->parent_irq);
iomemtype = cpu_register_io_memory(mv88w8618_pic_readfn,
mv88w8618_pic_writefn, s);
mv88w8618_pic_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype);
return 0;
}
@ -886,7 +889,8 @@ static int mv88w8618_pit_init(SysBusDevice *dev)
}
iomemtype = cpu_register_io_memory(mv88w8618_pit_readfn,
mv88w8618_pit_writefn, s);
mv88w8618_pit_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MP_PIT_SIZE, iomemtype);
return 0;
}
@ -976,7 +980,8 @@ static int mv88w8618_flashcfg_init(SysBusDevice *dev)
s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
iomemtype = cpu_register_io_memory(mv88w8618_flashcfg_readfn,
mv88w8618_flashcfg_writefn, s);
mv88w8618_flashcfg_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MP_FLASHCFG_SIZE, iomemtype);
return 0;
}
@ -1037,7 +1042,8 @@ static void musicpal_misc_init(void)
int iomemtype;
iomemtype = cpu_register_io_memory(musicpal_misc_readfn,
musicpal_misc_writefn, NULL);
musicpal_misc_writefn, NULL,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype);
}
@ -1082,7 +1088,8 @@ static int mv88w8618_wlan_init(SysBusDevice *dev)
int iomemtype;
iomemtype = cpu_register_io_memory(mv88w8618_wlan_readfn,
mv88w8618_wlan_writefn, NULL);
mv88w8618_wlan_writefn, NULL,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MP_WLAN_SIZE, iomemtype);
return 0;
}
@ -1293,7 +1300,8 @@ static int musicpal_gpio_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
iomemtype = cpu_register_io_memory(musicpal_gpio_readfn,
musicpal_gpio_writefn, s);
musicpal_gpio_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MP_GPIO_SIZE, iomemtype);
qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));

3
hw/omap.h
View file

@ -1129,7 +1129,8 @@ inline static int debug_register_io_memory(CPUReadMemoryFunc * const *mem_read,
s->mem_write = mem_write;
s->opaque = opaque;
s->in = 0;
return cpu_register_io_memory(io_readfn, io_writefn, s);
return cpu_register_io_memory(io_readfn, io_writefn, s,
DEVICE_NATIVE_ENDIAN);
}
# define cpu_register_io_memory debug_register_io_memory
# endif

42
hw/omap1.c
View file

@ -264,7 +264,7 @@ static struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
omap_timer_clk_setup(s);
iomemtype = cpu_register_io_memory(omap_mpu_timer_readfn,
omap_mpu_timer_writefn, s);
omap_mpu_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x100, iomemtype);
return s;
@ -387,7 +387,7 @@ static struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
omap_timer_clk_setup(&s->timer);
iomemtype = cpu_register_io_memory(omap_wd_timer_readfn,
omap_wd_timer_writefn, s);
omap_wd_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x100, iomemtype);
return s;
@ -489,7 +489,7 @@ static struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
omap_timer_clk_setup(&s->timer);
iomemtype = cpu_register_io_memory(omap_os_timer_readfn,
omap_os_timer_writefn, s);
omap_os_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
return s;
@ -716,7 +716,7 @@ static void omap_ulpd_pm_init(target_phys_addr_t base,
struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(omap_ulpd_pm_readfn,
omap_ulpd_pm_writefn, mpu);
omap_ulpd_pm_writefn, mpu, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
omap_ulpd_pm_reset(mpu);
@ -931,7 +931,7 @@ static void omap_pin_cfg_init(target_phys_addr_t base,
struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(omap_pin_cfg_readfn,
omap_pin_cfg_writefn, mpu);
omap_pin_cfg_writefn, mpu, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
omap_pin_cfg_reset(mpu);
@ -1001,7 +1001,7 @@ static CPUWriteMemoryFunc * const omap_id_writefn[] = {
static void omap_id_init(struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(omap_id_readfn,
omap_id_writefn, mpu);
omap_id_writefn, mpu, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory_offset(0xfffe1800, 0x800, iomemtype, 0xfffe1800);
cpu_register_physical_memory_offset(0xfffed400, 0x100, iomemtype, 0xfffed400);
if (!cpu_is_omap15xx(mpu))
@ -1084,7 +1084,7 @@ static void omap_mpui_init(target_phys_addr_t base,
struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(omap_mpui_readfn,
omap_mpui_writefn, mpu);
omap_mpui_writefn, mpu, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x100, iomemtype);
@ -1193,7 +1193,7 @@ static struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
omap_tipb_bridge_reset(s);
iomemtype = cpu_register_io_memory(omap_tipb_bridge_readfn,
omap_tipb_bridge_writefn, s);
omap_tipb_bridge_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x100, iomemtype);
return s;
@ -1299,7 +1299,7 @@ static void omap_tcmi_init(target_phys_addr_t base,
struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(omap_tcmi_readfn,
omap_tcmi_writefn, mpu);
omap_tcmi_writefn, mpu, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x100, iomemtype);
omap_tcmi_reset(mpu);
@ -1372,7 +1372,7 @@ static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base,
omap_clk clk)
{
int iomemtype = cpu_register_io_memory(omap_dpll_readfn,
omap_dpll_writefn, s);
omap_dpll_writefn, s, DEVICE_NATIVE_ENDIAN);
s->dpll = clk;
omap_dpll_reset(s);
@ -1776,8 +1776,10 @@ static void omap_clkm_init(target_phys_addr_t mpu_base,
target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
{
int iomemtype[2] = {
cpu_register_io_memory(omap_clkm_readfn, omap_clkm_writefn, s),
cpu_register_io_memory(omap_clkdsp_readfn, omap_clkdsp_writefn, s),
cpu_register_io_memory(omap_clkm_readfn, omap_clkm_writefn, s,
DEVICE_NATIVE_ENDIAN),
cpu_register_io_memory(omap_clkdsp_readfn, omap_clkdsp_writefn, s,
DEVICE_NATIVE_ENDIAN),
};
s->clkm.arm_idlect1 = 0x03ff;
@ -2031,7 +2033,7 @@ struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
omap_mpuio_reset(s);
iomemtype = cpu_register_io_memory(omap_mpuio_readfn,
omap_mpuio_writefn, s);
omap_mpuio_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]);
@ -2216,7 +2218,7 @@ struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
omap_uwire_reset(s);
iomemtype = cpu_register_io_memory(omap_uwire_readfn,
omap_uwire_writefn, s);
omap_uwire_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
return s;
@ -2317,7 +2319,7 @@ static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
omap_pwl_reset(s);
iomemtype = cpu_register_io_memory(omap_pwl_readfn,
omap_pwl_writefn, s);
omap_pwl_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]);
@ -2412,7 +2414,7 @@ static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
omap_pwt_reset(s);
iomemtype = cpu_register_io_memory(omap_pwt_readfn,
omap_pwt_writefn, s);
omap_pwt_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
}
@ -2825,7 +2827,7 @@ static struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
omap_rtc_reset(s);
iomemtype = cpu_register_io_memory(omap_rtc_readfn,
omap_rtc_writefn, s);
omap_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
return s;
@ -3347,7 +3349,7 @@ struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
omap_mcbsp_reset(s);
iomemtype = cpu_register_io_memory(omap_mcbsp_readfn,
omap_mcbsp_writefn, s);
omap_mcbsp_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
return s;
@ -3519,7 +3521,7 @@ static struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
omap_lpg_reset(s);
iomemtype = cpu_register_io_memory(omap_lpg_readfn,
omap_lpg_writefn, s);
omap_lpg_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]);
@ -3552,7 +3554,7 @@ static CPUWriteMemoryFunc * const omap_mpui_io_writefn[] = {
static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu)
{
int iomemtype = cpu_register_io_memory(omap_mpui_io_readfn,
omap_mpui_io_writefn, mpu);
omap_mpui_io_writefn, mpu, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype);
}

4
hw/omap2.c
View file

@ -600,7 +600,7 @@ static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
AUD_register_card("OMAP EAC", &s->codec.card);
iomemtype = cpu_register_io_memory(omap_eac_readfn,
omap_eac_writefn, s);
omap_eac_writefn, s, DEVICE_NATIVE_ENDIAN);
omap_l4_attach(ta, 0, iomemtype);
return s;
@ -788,7 +788,7 @@ static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
omap_l4_attach(ta, 0, iomemtype);
iomemtype = cpu_register_io_memory(omap_sti_fifo_readfn,
omap_sti_fifo_writefn, s);
omap_sti_fifo_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(channel_base, 0x10000, iomemtype);
return s;

4
hw/omap_dma.c
View file

@ -1659,7 +1659,7 @@ struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
omap_dma_clk_update(s, 0, 1);
iomemtype = cpu_register_io_memory(omap_dma_readfn,
omap_dma_writefn, s);
omap_dma_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, memsize, iomemtype);
mpu->drq = s->dma->drq;
@ -2066,7 +2066,7 @@ struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
omap_dma_clk_update(s, 0, !!s->dma->freq);
iomemtype = cpu_register_io_memory(omap_dma4_readfn,
omap_dma4_writefn, s);
omap_dma4_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x1000, iomemtype);
mpu->drq = s->dma->drq;

2
hw/omap_dss.c
View file

@ -1045,7 +1045,7 @@ struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
iomemtype[3] = l4_register_io_memory(omap_venc1_readfn,
omap_venc1_writefn, s);
iomemtype[4] = cpu_register_io_memory(omap_im3_readfn,
omap_im3_writefn, s);
omap_im3_writefn, s, DEVICE_NATIVE_ENDIAN);
omap_l4_attach(ta, 0, iomemtype[0]);
omap_l4_attach(ta, 1, iomemtype[1]);
omap_l4_attach(ta, 2, iomemtype[2]);

2
hw/omap_gpio.c
View file

@ -183,7 +183,7 @@ struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
omap_gpio_reset(s);
iomemtype = cpu_register_io_memory(omap_gpio_readfn,
omap_gpio_writefn, s);
omap_gpio_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x1000, iomemtype);
return s;

2
hw/omap_gpmc.c
View file

@ -390,7 +390,7 @@ struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq)
omap_gpmc_reset(s);
iomemtype = cpu_register_io_memory(omap_gpmc_readfn,
omap_gpmc_writefn, s);
omap_gpmc_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x1000, iomemtype);
return s;

2
hw/omap_i2c.c
View file

@ -437,7 +437,7 @@ struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
omap_i2c_reset(s);
iomemtype = cpu_register_io_memory(omap_i2c_readfn,
omap_i2c_writefn, s);
omap_i2c_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
return s;

4
hw/omap_intc.c
View file

@ -371,7 +371,7 @@ struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
omap_inth_reset(s);
iomemtype = cpu_register_io_memory(omap_inth_readfn,
omap_inth_writefn, s);
omap_inth_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, size, iomemtype);
return s;
@ -591,7 +591,7 @@ struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
omap_inth_reset(s);
iomemtype = cpu_register_io_memory(omap2_inth_readfn,
omap2_inth_writefn, s);
omap2_inth_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, size, iomemtype);
return s;

5
hw/omap_l4.c
View file

@ -107,7 +107,8 @@ int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read,
CPUWriteMemoryFunc * const *mem_write,
void *opaque)
{
return cpu_register_io_memory(mem_read, mem_write, opaque);
return cpu_register_io_memory(mem_read, mem_write, opaque,
DEVICE_NATIVE_ENDIAN);
}
#endif
@ -131,7 +132,7 @@ struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num)
omap_cpu_io_entry =
cpu_register_io_memory(omap_l4_io_readfn,
omap_l4_io_writefn, bus);
omap_l4_io_writefn, bus, DEVICE_NATIVE_ENDIAN);
# define L4_PAGES (0xb4000 / TARGET_PAGE_SIZE)
omap_l4_io_readb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
omap_l4_io_readh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);

2
hw/omap_lcdc.c
View file

@ -450,7 +450,7 @@ struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
omap_lcdc_reset(s);
iomemtype = cpu_register_io_memory(omap_lcdc_readfn,
omap_lcdc_writefn, s);
omap_lcdc_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x100, iomemtype);
s->state = graphic_console_init(omap_update_display,

2
hw/omap_mmc.c
View file

@ -587,7 +587,7 @@ struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
omap_mmc_reset(s);
iomemtype = cpu_register_io_memory(omap_mmc_readfn,
omap_mmc_writefn, s);
omap_mmc_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x800, iomemtype);
/* Instantiate the storage */

2
hw/omap_sdrc.c
View file

@ -158,7 +158,7 @@ struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base)
omap_sdrc_reset(s);
iomemtype = cpu_register_io_memory(omap_sdrc_readfn,
omap_sdrc_writefn, s);
omap_sdrc_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x1000, iomemtype);
return s;

15
hw/omap_sx1.c
View file

@ -143,12 +143,15 @@ static void sx1_init(ram_addr_t ram_size,
qemu_ram_alloc(NULL, "omap_sx1.flash0-0",
flash_size) | IO_MEM_ROM);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs0val);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs0val,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_CS0_BASE + flash_size,
OMAP_CS0_SIZE - flash_size, io);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs2val);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs2val,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_CS2_BASE, OMAP_CS2_SIZE, io);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs3val);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs3val,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_CS3_BASE, OMAP_CS3_SIZE, io);
fl_idx = 0;
@ -175,7 +178,8 @@ static void sx1_init(ram_addr_t ram_size,
cpu_register_physical_memory(OMAP_CS1_BASE, flash1_size,
qemu_ram_alloc(NULL, "omap_sx1.flash1-0",
flash1_size) | IO_MEM_ROM);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_CS1_BASE + flash1_size,
OMAP_CS1_SIZE - flash1_size, io);
@ -189,7 +193,8 @@ static void sx1_init(ram_addr_t ram_size,
}
fl_idx++;
} else {
io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_CS1_BASE, OMAP_CS1_SIZE, io);
}

2
hw/omap_uart.c
View file

@ -170,7 +170,7 @@ struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
struct omap_uart_s *s = omap_uart_init(base, irq,
fclk, iclk, txdma, rxdma, label, chr);
int iomemtype = cpu_register_io_memory(omap_uart_readfn,
omap_uart_writefn, s);
omap_uart_writefn, s, DEVICE_NATIVE_ENDIAN);
s->ta = ta;

2
hw/onenand.c
View file

@ -630,7 +630,7 @@ void *onenand_init(uint32_t id, int regshift, qemu_irq irq)
s->blockwp = qemu_malloc(s->blocks);
s->density_mask = (id & (1 << 11)) ? (1 << (6 + ((id >> 12) & 7))) : 0;
s->iomemtype = cpu_register_io_memory(onenand_readfn,
onenand_writefn, s);
onenand_writefn, s, DEVICE_NATIVE_ENDIAN);
if (!dinfo)
s->image = memset(qemu_malloc(size + (size >> 5)),
0xff, size + (size >> 5));

10
hw/openpic.c
View file

@ -1035,7 +1035,8 @@ static void openpic_map(PCIDevice *pci_dev, int region_num,
cpu_register_physical_memory(addr, 0x40000, opp->mem_index);
#if 0 // Don't implement ISU for now
opp_io_memory = cpu_register_io_memory(openpic_src_read,
openpic_src_write);
openpic_src_write, NULL
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(isu_base, 0x20 * (EXT_IRQ + 2),
opp_io_memory);
#endif
@ -1202,8 +1203,8 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
} else {
opp = qemu_mallocz(sizeof(openpic_t));
}
opp->mem_index = cpu_register_io_memory(openpic_read,
openpic_write, opp);
opp->mem_index = cpu_register_io_memory(openpic_read, openpic_write, opp,
DEVICE_NATIVE_ENDIAN);
// isu_base &= 0xFFFC0000;
opp->nb_cpus = nb_cpus;
@ -1671,7 +1672,8 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) {
int mem_index;
mem_index = cpu_register_io_memory(list[i].read, list[i].write, mpp);
mem_index = cpu_register_io_memory(list[i].read, list[i].write, mpp,
DEVICE_NATIVE_ENDIAN);
if (mem_index < 0) {
goto free;
}

12
hw/palm.c
View file

@ -216,14 +216,18 @@ static void palmte_init(ram_addr_t ram_size,
qemu_ram_alloc(NULL, "palmte.flash",
flash_size) | IO_MEM_ROM);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs0val);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs0val,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_CS0_BASE + flash_size,
OMAP_CS0_SIZE - flash_size, io);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_CS1_BASE, OMAP_CS1_SIZE, io);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs2val);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs2val,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_CS2_BASE, OMAP_CS2_SIZE, io);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs3val);
io = cpu_register_io_memory(static_readfn, static_writefn, &cs3val,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(OMAP_CS3_BASE, OMAP_CS3_SIZE, io);
palmte_microwire_setup(cpu);

3
hw/parallel.c
View file

@ -577,7 +577,8 @@ ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq
s->it_shift = it_shift;
qemu_register_reset(parallel_reset, s);
io_sw = cpu_register_io_memory(parallel_mm_read_sw, parallel_mm_write_sw, s);
io_sw = cpu_register_io_memory(parallel_mm_read_sw, parallel_mm_write_sw,
s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 8 << it_shift, io_sw);
return s;
}

3
hw/pcie_host.c
View file

@ -137,7 +137,8 @@ int pcie_host_init(PCIExpressHost *e)
{
e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
e->mmio_index =
cpu_register_io_memory(pcie_mmcfg_read, pcie_mmcfg_write, e);
cpu_register_io_memory(pcie_mmcfg_read, pcie_mmcfg_write, e,
DEVICE_NATIVE_ENDIAN);
if (e->mmio_index < 0) {
return -1;
}

3
hw/pckbd.c
View file

@ -436,7 +436,8 @@ void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
s->mask = mask;
vmstate_register(NULL, 0, &vmstate_kbd, s);
s_io_memory = cpu_register_io_memory(kbd_mm_read, kbd_mm_write, s);
s_io_memory = cpu_register_io_memory(kbd_mm_read, kbd_mm_write, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, size, s_io_memory);
s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);

3
hw/pcnet-pci.c
View file

@ -294,7 +294,8 @@ static int pci_pcnet_init(PCIDevice *pci_dev)
/* Handler for memory-mapped I/O */
s->mmio_index =
cpu_register_io_memory(pcnet_mmio_read, pcnet_mmio_write, &d->state);
cpu_register_io_memory(pcnet_mmio_read, pcnet_mmio_write, &d->state,
DEVICE_NATIVE_ENDIAN);
pci_register_bar(pci_dev, 0, PCNET_IOPORT_SIZE,
PCI_BASE_ADDRESS_SPACE_IO, pcnet_ioport_map);

6
hw/pflash_cfi01.c
View file

@ -600,10 +600,12 @@ pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
pfl->storage = qemu_get_ram_ptr(off);
if (be) {
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be,
pflash_write_ops_be, pfl);
pflash_write_ops_be, pfl,
DEVICE_NATIVE_ENDIAN);
} else {
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le,
pflash_write_ops_le, pfl);
pflash_write_ops_le, pfl,
DEVICE_NATIVE_ENDIAN);
}
pfl->off = off;
cpu_register_physical_memory(base, total_len,

4
hw/pflash_cfi02.c
View file

@ -619,11 +619,11 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
if (be) {
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be,
pflash_write_ops_be,
pfl);
pfl, DEVICE_NATIVE_ENDIAN);
} else {
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le,
pflash_write_ops_le,
pfl);
pfl, DEVICE_NATIVE_ENDIAN);
}
pfl->off = off;
pfl->base = base;

3
hw/pl011.c
View file

@ -292,7 +292,8 @@ static int pl011_init(SysBusDevice *dev, const unsigned char *id)
pl011_state *s = FROM_SYSBUS(pl011_state, dev);
iomemtype = cpu_register_io_memory(pl011_readfn,
pl011_writefn, s);
pl011_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000,iomemtype);
sysbus_init_irq(dev, &s->irq);
s->id = id;

3
hw/pl022.c
View file

@ -294,7 +294,8 @@ static int pl022_init(SysBusDevice *dev)
int iomemtype;
iomemtype = cpu_register_io_memory(pl022_readfn,
pl022_writefn, s);
pl022_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
sysbus_init_irq(dev, &s->irq);
s->ssi = ssi_create_bus(&dev->qdev, "ssi");

3
hw/pl031.c
View file

@ -189,7 +189,8 @@ static int pl031_init(SysBusDevice *dev)
pl031_state *s = FROM_SYSBUS(pl031_state, dev);
struct tm tm;
iomemtype = cpu_register_io_memory(pl031_readfn, pl031_writefn, s);
iomemtype = cpu_register_io_memory(pl031_readfn, pl031_writefn, s,
DEVICE_NATIVE_ENDIAN);
if (iomemtype == -1) {
hw_error("pl031_init: Can't register I/O memory\n");
}

3
hw/pl050.c
View file

@ -128,7 +128,8 @@ static int pl050_init(SysBusDevice *dev, int is_mouse)
int iomemtype;
iomemtype = cpu_register_io_memory(pl050_readfn,
pl050_writefn, s);
pl050_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
sysbus_init_irq(dev, &s->irq);
s->is_mouse = is_mouse;

3
hw/pl061.c
View file

@ -297,7 +297,8 @@ static int pl061_init(SysBusDevice *dev)
pl061_state *s = FROM_SYSBUS(pl061_state, dev);
iomemtype = cpu_register_io_memory(pl061_readfn,
pl061_writefn, s);
pl061_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
sysbus_init_irq(dev, &s->irq);
qdev_init_gpio_in(&dev->qdev, pl061_set_irq, 8);

3
hw/pl080.c
View file

@ -325,7 +325,8 @@ static int pl08x_init(SysBusDevice *dev, int nchannels)
pl080_state *s = FROM_SYSBUS(pl080_state, dev);
iomemtype = cpu_register_io_memory(pl080_readfn,
pl080_writefn, s);
pl080_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
sysbus_init_irq(dev, &s->irq);
s->nchannels = nchannels;

3
hw/pl110.c
View file

@ -358,7 +358,8 @@ static int pl110_init(SysBusDevice *dev)
int iomemtype;
iomemtype = cpu_register_io_memory(pl110_readfn,
pl110_writefn, s);
pl110_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
sysbus_init_irq(dev, &s->irq);
s->ds = graphic_console_init(pl110_update_display,

4
hw/pl181.c
View file

@ -451,8 +451,8 @@ static int pl181_init(SysBusDevice *dev)
pl181_state *s = FROM_SYSBUS(pl181_state, dev);
BlockDriverState *bd;
iomemtype = cpu_register_io_memory(pl181_readfn,
pl181_writefn, s);
iomemtype = cpu_register_io_memory(pl181_readfn, pl181_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
sysbus_init_irq(dev, &s->irq[0]);
sysbus_init_irq(dev, &s->irq[1]);

3
hw/pl190.c
View file

@ -233,7 +233,8 @@ static int pl190_init(SysBusDevice *dev)
int iomemtype;
iomemtype = cpu_register_io_memory(pl190_readfn,
pl190_writefn, s);
pl190_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
qdev_init_gpio_in(&dev->qdev, pl190_set_irq, 32);
sysbus_init_irq(dev, &s->irq);

6
hw/ppc405_boards.c
View file

@ -164,7 +164,8 @@ static void ref405ep_fpga_init (uint32_t base)
fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
fpga_memory = cpu_register_io_memory(ref405ep_fpga_read,
ref405ep_fpga_write, fpga);
ref405ep_fpga_write, fpga,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00000100, fpga_memory);
qemu_register_reset(&ref405ep_fpga_reset, fpga);
}
@ -488,7 +489,8 @@ static void taihu_cpld_init (uint32_t base)
cpld = qemu_mallocz(sizeof(taihu_cpld_t));
cpld_memory = cpu_register_io_memory(taihu_cpld_read,
taihu_cpld_write, cpld);
taihu_cpld_write, cpld,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00000100, cpld_memory);
qemu_register_reset(&taihu_cpld_reset, cpld);
}

11
hw/ppc405_uc.c
View file

@ -383,7 +383,8 @@ static void ppc4xx_opba_init(target_phys_addr_t base)
#ifdef DEBUG_OPBA
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
io = cpu_register_io_memory(opba_read, opba_write, opba);
io = cpu_register_io_memory(opba_read, opba_write, opba,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x002, io);
qemu_register_reset(ppc4xx_opba_reset, opba);
}
@ -809,7 +810,8 @@ static void ppc405_gpio_init(target_phys_addr_t base)
#ifdef DEBUG_GPIO
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio);
io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x038, io);
qemu_register_reset(&ppc405_gpio_reset, gpio);
}
@ -1218,7 +1220,8 @@ static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
#ifdef DEBUG_I2C
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
io = cpu_register_io_memory(i2c_read, i2c_write, i2c);
io = cpu_register_io_memory(i2c_read, i2c_write, i2c,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x011, io);
qemu_register_reset(ppc4xx_i2c_reset, i2c);
}
@ -1501,7 +1504,7 @@ static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
#ifdef DEBUG_GPT
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
io = cpu_register_io_memory(gpt_read, gpt_write, gpt);
io = cpu_register_io_memory(gpt_read, gpt_write, gpt, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x0d4, io);
qemu_register_reset(ppc4xx_gpt_reset, gpt);
}

6
hw/ppc4xx_pci.c
View file

@ -372,7 +372,8 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
/* CFGADDR */
index = cpu_register_io_memory(pci4xx_cfgaddr_read,
pci4xx_cfgaddr_write, controller);
pci4xx_cfgaddr_write, controller,
DEVICE_NATIVE_ENDIAN);
if (index < 0)
goto free;
cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index);
@ -384,7 +385,8 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
cpu_register_physical_memory(config_space + PCIC0_CFGDATA, 4, index);
/* Internal registers */
index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller);
index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller,
DEVICE_NATIVE_ENDIAN);
if (index < 0)
goto free;
cpu_register_physical_memory(registers, PCI_REG_SIZE, index);

3
hw/ppc_newworld.c
View file

@ -260,7 +260,8 @@ static void ppc_core99_init (ram_addr_t ram_size,
isa_mmio_init(0xf2000000, 0x00800000, 1);
/* UniN init */
unin_memory = cpu_register_io_memory(unin_read, unin_write, NULL);
unin_memory = cpu_register_io_memory(unin_read, unin_write, NULL,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory);
openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));

8
hw/ppc_prep.c
View file

@ -690,7 +690,8 @@ static void ppc_prep_init (ram_addr_t ram_size,
// pci_bus = i440fx_init();
/* Register 8 MB of ISA IO space (needed for non-contiguous map) */
PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read,
PPC_prep_io_write, sysctrl);
PPC_prep_io_write, sysctrl,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
/* init basic PC hardware */
@ -755,12 +756,13 @@ static void ppc_prep_init (ram_addr_t ram_size,
register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
/* PCI intack location */
PPC_io_memory = cpu_register_io_memory(PPC_intack_read,
PPC_intack_write, NULL);
PPC_intack_write, NULL,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
/* PowerPC control and status register group */
#if 0
PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write,
NULL);
NULL, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
#endif

3
hw/ppce500_pci.c
View file

@ -304,7 +304,8 @@ PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers)
cpu_register_physical_memory(registers + PCIE500_CFGDATA, 4, index);
index = cpu_register_io_memory(e500_pci_reg_read,
e500_pci_reg_write, controller);
e500_pci_reg_write, controller,
DEVICE_NATIVE_ENDIAN);
if (index < 0)
goto free;
cpu_register_physical_memory(registers + PCIE500_REG_BASE,

3
hw/prep_pci.c
View file

@ -125,7 +125,8 @@ PCIBus *pci_prep_init(qemu_irq *pic)
pci_host_data_register_ioport(0xcfc, s);
PPC_io_memory = cpu_register_io_memory(PPC_PCIIO_read,
PPC_PCIIO_write, s);
PPC_PCIIO_write, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
/* PCI host bridge */

25
hw/pxa2xx.c
View file

@ -859,7 +859,8 @@ static int pxa2xx_ssp_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
iomemtype = cpu_register_io_memory(pxa2xx_ssp_readfn,
pxa2xx_ssp_writefn, s);
pxa2xx_ssp_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
register_savevm(&dev->qdev, "pxa2xx_ssp", -1, 0,
pxa2xx_ssp_save, pxa2xx_ssp_load, s);
@ -1512,7 +1513,7 @@ PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
s->offset = base - (base & (~region_size) & TARGET_PAGE_MASK);
iomemtype = cpu_register_io_memory(pxa2xx_i2c_readfn,
pxa2xx_i2c_writefn, s);
pxa2xx_i2c_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base & ~region_size,
region_size + 1, iomemtype);
@ -1749,7 +1750,7 @@ static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base,
pxa2xx_i2s_reset(s);
iomemtype = cpu_register_io_memory(pxa2xx_i2s_readfn,
pxa2xx_i2s_writefn, s);
pxa2xx_i2s_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x100000, iomemtype);
register_savevm(NULL, "pxa2xx_i2s", base, 0,
@ -2009,7 +2010,7 @@ static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base,
pxa2xx_fir_reset(s);
iomemtype = cpu_register_io_memory(pxa2xx_fir_readfn,
pxa2xx_fir_writefn, s);
pxa2xx_fir_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x1000, iomemtype);
if (chr)
@ -2102,7 +2103,7 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
s->clkcfg = 0x00000009; /* Turbo mode active */
iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,
pxa2xx_cm_writefn, s);
pxa2xx_cm_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
register_savevm(NULL, "pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
@ -2113,13 +2114,13 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
s->mm_regs[MDREFR >> 2] = 0x03ca4000;
s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,
pxa2xx_mm_writefn, s);
pxa2xx_mm_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
register_savevm(NULL, "pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
s->pm_base = 0x40f00000;
iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,
pxa2xx_pm_writefn, s);
pxa2xx_pm_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
register_savevm(NULL, "pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
@ -2142,7 +2143,7 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
s->rtc_base = 0x40900000;
iomemtype = cpu_register_io_memory(pxa2xx_rtc_readfn,
pxa2xx_rtc_writefn, s);
pxa2xx_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
pxa2xx_rtc_init(s);
register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save,
@ -2225,7 +2226,7 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
s->clkcfg = 0x00000009; /* Turbo mode active */
iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,
pxa2xx_cm_writefn, s);
pxa2xx_cm_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
register_savevm(NULL, "pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
@ -2236,13 +2237,13 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
s->mm_regs[MDREFR >> 2] = 0x03ca4000;
s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,
pxa2xx_mm_writefn, s);
pxa2xx_mm_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
register_savevm(NULL, "pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
s->pm_base = 0x40f00000;
iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,
pxa2xx_pm_writefn, s);
pxa2xx_pm_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
register_savevm(NULL, "pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
@ -2265,7 +2266,7 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
s->rtc_base = 0x40900000;
iomemtype = cpu_register_io_memory(pxa2xx_rtc_readfn,
pxa2xx_rtc_writefn, s);
pxa2xx_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
pxa2xx_rtc_init(s);
register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save,

2
hw/pxa2xx_dma.c
View file

@ -504,7 +504,7 @@ static PXA2xxDMAState *pxa2xx_dma_init(target_phys_addr_t base,
memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS);
iomemtype = cpu_register_io_memory(pxa2xx_dma_readfn,
pxa2xx_dma_writefn, s);
pxa2xx_dma_writefn, s, DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00010000, iomemtype);
register_savevm(NULL, "pxa2xx_dma", 0, 0, pxa2xx_dma_save, pxa2xx_dma_load, s);

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