mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-10-08 20:19:52 +00:00
ab3d207fe8
When shutting down the machine running a mainline Linux kernel, the following error happens: $ build/riscv64-softmmu/qemu-system-riscv64 -bios default -M virt \ -display none -initrd rootfs.cpio -kernel Image -m 512m \ -nodefaults -serial mon:stdio ... Requesting system poweroff [ 4.999630] reboot: Power down sbi_trap_error: hart0: trap handler failed (error -2) sbi_trap_error: hart0: mcause=0x0000000000000007 mtval=0x0000000000100000 sbi_trap_error: hart0: mepc=0x000000008000d4cc mstatus=0x0000000000001822 sbi_trap_error: hart0: ra=0x000000008000999e sp=0x0000000080015c78 sbi_trap_error: hart0: gp=0xffffffe000e76610 tp=0xffffffe0081b89c0 sbi_trap_error: hart0: s0=0x0000000080015c88 s1=0x0000000000000040 sbi_trap_error: hart0: a0=0x0000000000000000 a1=0x0000000080004024 sbi_trap_error: hart0: a2=0x0000000080004024 a3=0x0000000080004024 sbi_trap_error: hart0: a4=0x0000000000100000 a5=0x0000000000005555 sbi_trap_error: hart0: a6=0x0000000000004024 a7=0x0000000080011158 sbi_trap_error: hart0: s2=0x0000000000000000 s3=0x0000000080016000 sbi_trap_error: hart0: s4=0x0000000000000000 s5=0x0000000000000000 sbi_trap_error: hart0: s6=0x0000000000000001 s7=0x0000000000000000 sbi_trap_error: hart0: s8=0x0000000000000000 s9=0x0000000000000000 sbi_trap_error: hart0: s10=0x0000000000000000 s11=0x0000000000000008 sbi_trap_error: hart0: t0=0x0000000000000000 t1=0x0000000000000000 sbi_trap_error: hart0: t2=0x0000000000000000 t3=0x0000000000000000 sbi_trap_error: hart0: t4=0x0000000000000000 t5=0x0000000000000000 sbi_trap_error: hart0: t6=0x0000000000000000 The kernel does a 16-bit write when powering off the machine, which was allowed before commit5d971f9e67
("memory: Revert "memory: accept mismatching sizes in memory_region_access_valid""). Make min_access_size match reality so that the machine can shut down properly now. Cc: qemu-stable@nongnu.org Fixes:88a07990fa
("SiFive RISC-V Test Finisher") Fixes:5d971f9e67
("memory: Revert "memory: accept mismatching sizes in memory_region_access_valid"") Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200901055822.2721209-1-natechancellor@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
101 lines
2.7 KiB
C
101 lines
2.7 KiB
C
/*
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* QEMU SiFive Test Finisher
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*
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* Copyright (c) 2018 SiFive, Inc.
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*
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* Test finisher memory mapped device used to exit simulation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "sysemu/runstate.h"
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#include "hw/hw.h"
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#include "hw/riscv/sifive_test.h"
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static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
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{
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return 0;
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}
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static void sifive_test_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size)
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{
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if (addr == 0) {
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int status = val64 & 0xffff;
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int code = (val64 >> 16) & 0xffff;
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switch (status) {
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case FINISHER_FAIL:
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exit(code);
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case FINISHER_PASS:
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exit(0);
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case FINISHER_RESET:
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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return;
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default:
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break;
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}
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}
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qemu_log_mask(LOG_GUEST_ERROR, "%s: write: addr=0x%x val=0x%016" PRIx64 "\n",
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__func__, (int)addr, val64);
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}
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static const MemoryRegionOps sifive_test_ops = {
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.read = sifive_test_read,
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.write = sifive_test_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 2,
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.max_access_size = 4
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}
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};
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static void sifive_test_init(Object *obj)
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{
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SiFiveTestState *s = SIFIVE_TEST(obj);
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memory_region_init_io(&s->mmio, obj, &sifive_test_ops, s,
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TYPE_SIFIVE_TEST, 0x1000);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
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}
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static const TypeInfo sifive_test_info = {
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.name = TYPE_SIFIVE_TEST,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(SiFiveTestState),
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.instance_init = sifive_test_init,
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};
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static void sifive_test_register_types(void)
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{
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type_register_static(&sifive_test_info);
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}
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type_init(sifive_test_register_types)
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/*
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* Create Test device.
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*/
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DeviceState *sifive_test_create(hwaddr addr)
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{
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DeviceState *dev = qdev_new(TYPE_SIFIVE_TEST);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
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return dev;
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}
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