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https://gitlab.com/qemu-project/qemu
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4100d5e6dc
RISC-V machines do not instantiate RISC-V CPUs directly, instead they do that via the hart array. Add a new property for the reset vector address to allow the value to be passed to the CPU, before CPU is realized. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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.. | ||
boot.c | ||
Kconfig | ||
meson.build | ||
numa.c | ||
opentitan.c | ||
riscv_hart.c | ||
riscv_htif.c | ||
sifive_clint.c | ||
sifive_e.c | ||
sifive_e_prci.c | ||
sifive_gpio.c | ||
sifive_plic.c | ||
sifive_test.c | ||
sifive_u.c | ||
sifive_u_otp.c | ||
sifive_u_prci.c | ||
sifive_uart.c | ||
spike.c | ||
trace-events | ||
trace.h | ||
virt.c |