mirror of
https://gitlab.com/qemu-project/qemu
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6aa4f1d15c
Precursor to moving new_value from the global state to DisasContext USR will need to stay in the global state because some helpers will set it's value Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-17-tsimpson@quicinc.com>
65 lines
3.1 KiB
C
65 lines
3.1 KiB
C
/*
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* Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HEXAGON_GENPTR_H
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#define HEXAGON_GENPTR_H
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#include "insn.h"
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#include "tcg/tcg.h"
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#include "translate.h"
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extern const SemanticInsn opcode_genptr[];
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void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot);
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void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot);
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void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot);
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void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot);
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void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, uint32_t slot);
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void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot);
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void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot);
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void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot);
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void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, uint32_t slot);
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TCGv gen_read_reg(TCGv result, int num);
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TCGv gen_read_preg(TCGv pred, uint8_t num);
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TCGv get_result_gpr(DisasContext *ctx, int rnum);
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TCGv get_result_pred(DisasContext *ctx, int pnum);
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void gen_log_reg_write(DisasContext *ctx, int rnum, TCGv val);
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void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val);
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void gen_set_usr_field(DisasContext *ctx, int field, TCGv val);
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void gen_set_usr_fieldi(DisasContext *ctx, int field, int x);
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void gen_set_usr_field_if(DisasContext *ctx, int field, TCGv val);
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void gen_sat_i32(TCGv dest, TCGv source, int width);
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void gen_sat_i32_ovfl(TCGv ovfl, TCGv dest, TCGv source, int width);
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void gen_satu_i32(TCGv dest, TCGv source, int width);
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void gen_satu_i32_ovfl(TCGv ovfl, TCGv dest, TCGv source, int width);
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void gen_sat_i64(TCGv_i64 dest, TCGv_i64 source, int width);
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void gen_sat_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width);
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void gen_satu_i64(TCGv_i64 dest, TCGv_i64 source, int width);
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void gen_satu_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width);
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void gen_add_sat_i64(DisasContext *ctx, TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b);
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TCGv gen_8bitsof(TCGv result, TCGv value);
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void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src);
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TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign);
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TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign);
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TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign);
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void gen_set_half(int N, TCGv result, TCGv src);
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void gen_set_half_i64(int N, TCGv_i64 result, TCGv src);
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void probe_noshuf_load(TCGv va, int s, int mi);
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extern const target_ulong reg_immut_masks[TOTAL_PER_THREAD_REGS];
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#endif
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