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Hexagon (target/hexagon) Make special new_value for USR
Precursor to moving new_value from the global state to DisasContext USR will need to stay in the global state because some helpers will set it's value Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-17-tsimpson@quicinc.com>
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@ -186,7 +186,7 @@ We also generate an analyze_<tag> function for each instruction. Currently,
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these functions record the writes to registers by calling ctx_log_*. During
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gen_start_packet, we invoke the analyze_<tag> function for each instruction in
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the packet, and we mark the implicit writes. After the analysis is performed,
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we initialize hex_new_value for each of the predicated assignments.
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we initialize the result register for each of the predicated assignments.
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In addition to instruction semantics, we use a generator to create the decode
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tree. This generation is also a two step process. The first step is to run
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@ -90,6 +90,7 @@ typedef struct CPUArchState {
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uint8_t slot_cancelled;
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target_ulong new_value[TOTAL_PER_THREAD_REGS];
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target_ulong new_value_usr;
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/*
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* Only used when HEX_DEBUG is on, but unconditionally included
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@ -190,7 +190,7 @@ def genptr_decl_new(f, tag, regtype, regid, regno):
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if regid in {"s", "t"}:
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f.write(
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f" TCGv {regtype}{regid}N = "
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f"hex_new_value[insn->regno[{regno}]];\n"
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f"get_result_gpr(ctx, insn->regno[{regno}]);\n"
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)
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else:
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print("Bad register parse: ", regtype, regid)
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@ -68,10 +68,14 @@ static inline void gen_masked_reg_write(TCGv new_val, TCGv cur_val,
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}
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}
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static TCGv get_result_gpr(DisasContext *ctx, int rnum)
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TCGv get_result_gpr(DisasContext *ctx, int rnum)
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{
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if (ctx->need_commit) {
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return hex_new_value[rnum];
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if (rnum == HEX_REG_USR) {
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return hex_new_value_usr;
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} else {
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return hex_new_value[rnum];
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}
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} else {
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return hex_gpr[rnum];
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}
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@ -35,6 +35,7 @@ void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot);
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void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, uint32_t slot);
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TCGv gen_read_reg(TCGv result, int num);
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TCGv gen_read_preg(TCGv pred, uint8_t num);
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TCGv get_result_gpr(DisasContext *ctx, int rnum);
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TCGv get_result_pred(DisasContext *ctx, int pnum);
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void gen_log_reg_write(DisasContext *ctx, int rnum, TCGv val);
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void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val);
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@ -46,7 +46,7 @@
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#define SET_USR_FIELD(FIELD, VAL) \
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do { \
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if (pkt_need_commit) { \
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fINSERT_BITS(env->new_value[HEX_REG_USR], \
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fINSERT_BITS(env->new_value_usr, \
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reg_field_info[FIELD].width, \
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reg_field_info[FIELD].offset, (VAL)); \
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} else { \
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@ -45,6 +45,7 @@ TCGv hex_this_PC;
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TCGv hex_slot_cancelled;
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TCGv hex_branch_taken;
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TCGv hex_new_value[TOTAL_PER_THREAD_REGS];
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TCGv hex_new_value_usr;
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TCGv hex_reg_written[TOTAL_PER_THREAD_REGS];
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TCGv hex_new_pred_value[NUM_PREGS];
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TCGv hex_pred_written;
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@ -547,12 +548,12 @@ static void gen_start_packet(DisasContext *ctx)
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tcg_gen_movi_tl(hex_pred_written, 0);
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}
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/* Preload the predicated registers into hex_new_value[i] */
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/* Preload the predicated registers into get_result_gpr(ctx, i) */
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if (ctx->need_commit &&
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!bitmap_empty(ctx->predicated_regs, TOTAL_PER_THREAD_REGS)) {
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int i = find_first_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS);
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while (i < TOTAL_PER_THREAD_REGS) {
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tcg_gen_mov_tl(hex_new_value[i], hex_gpr[i]);
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tcg_gen_mov_tl(get_result_gpr(ctx, i), hex_gpr[i]);
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i = find_next_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS,
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i + 1);
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}
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@ -667,7 +668,7 @@ static void gen_reg_writes(DisasContext *ctx)
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for (i = 0; i < ctx->reg_log_idx; i++) {
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int reg_num = ctx->reg_log[i];
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tcg_gen_mov_tl(hex_gpr[reg_num], hex_new_value[reg_num]);
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tcg_gen_mov_tl(hex_gpr[reg_num], get_result_gpr(ctx, reg_num));
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/*
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* ctx->is_tight_loop is set when SA0 points to the beginning of the TB.
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@ -1180,10 +1181,14 @@ void hexagon_translate_init(void)
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offsetof(CPUHexagonState, gpr[i]),
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hexagon_regnames[i]);
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snprintf(new_value_names[i], NAME_LEN, "new_%s", hexagon_regnames[i]);
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hex_new_value[i] = tcg_global_mem_new(cpu_env,
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offsetof(CPUHexagonState, new_value[i]),
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new_value_names[i]);
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if (i == HEX_REG_USR) {
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hex_new_value[i] = NULL;
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} else {
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snprintf(new_value_names[i], NAME_LEN, "new_%s", hexagon_regnames[i]);
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hex_new_value[i] = tcg_global_mem_new(cpu_env,
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offsetof(CPUHexagonState, new_value[i]),
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new_value_names[i]);
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}
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if (HEX_DEBUG) {
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snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s",
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@ -1193,6 +1198,9 @@ void hexagon_translate_init(void)
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reg_written_names[i]);
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}
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}
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hex_new_value_usr = tcg_global_mem_new(cpu_env,
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offsetof(CPUHexagonState, new_value_usr), "new_value_usr");
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for (i = 0; i < NUM_PREGS; i++) {
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hex_pred[i] = tcg_global_mem_new(cpu_env,
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offsetof(CPUHexagonState, pred[i]),
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@ -191,6 +191,7 @@ extern TCGv hex_this_PC;
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extern TCGv hex_slot_cancelled;
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extern TCGv hex_branch_taken;
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extern TCGv hex_new_value[TOTAL_PER_THREAD_REGS];
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extern TCGv hex_new_value_usr;
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extern TCGv hex_reg_written[TOTAL_PER_THREAD_REGS];
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extern TCGv hex_new_pred_value[NUM_PREGS];
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extern TCGv hex_pred_written;
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