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https://gitlab.com/qemu-project/qemu
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2507c12ab0
As stated before, devices can be little, big or native endian. The target endianness is not of their concern, so we need to push things down a level. This patch adds a parameter to cpu_register_io_memory that allows a device to choose its endianness. For now, all devices simply choose native endian, because that's the same behavior as before. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
88 lines
2.6 KiB
C
88 lines
2.6 KiB
C
#include "rwhandler.h"
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#include "ioport.h"
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#include "cpu-all.h"
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#define RWHANDLER_WRITE(name, len, type) \
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static void name(void *opaque, type addr, uint32_t value) \
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{\
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struct ReadWriteHandler *handler = opaque;\
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handler->write(handler, addr, value, len);\
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}
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#define RWHANDLER_READ(name, len, type) \
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static uint32_t name(void *opaque, type addr) \
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{ \
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struct ReadWriteHandler *handler = opaque; \
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return handler->read(handler, addr, len); \
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}
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RWHANDLER_WRITE(cpu_io_memory_simple_writeb, 1, target_phys_addr_t);
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RWHANDLER_READ(cpu_io_memory_simple_readb, 1, target_phys_addr_t);
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RWHANDLER_WRITE(cpu_io_memory_simple_writew, 2, target_phys_addr_t);
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RWHANDLER_READ(cpu_io_memory_simple_readw, 2, target_phys_addr_t);
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RWHANDLER_WRITE(cpu_io_memory_simple_writel, 4, target_phys_addr_t);
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RWHANDLER_READ(cpu_io_memory_simple_readl, 4, target_phys_addr_t);
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static CPUWriteMemoryFunc * const cpu_io_memory_simple_write[] = {
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&cpu_io_memory_simple_writeb,
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&cpu_io_memory_simple_writew,
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&cpu_io_memory_simple_writel,
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};
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static CPUReadMemoryFunc * const cpu_io_memory_simple_read[] = {
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&cpu_io_memory_simple_readb,
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&cpu_io_memory_simple_readw,
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&cpu_io_memory_simple_readl,
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};
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int cpu_register_io_memory_simple(struct ReadWriteHandler *handler)
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{
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if (!handler->read || !handler->write) {
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return -1;
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}
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return cpu_register_io_memory(cpu_io_memory_simple_read,
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cpu_io_memory_simple_write,
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handler, DEVICE_NATIVE_ENDIAN);
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}
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RWHANDLER_WRITE(ioport_simple_writeb, 1, uint32_t);
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RWHANDLER_READ(ioport_simple_readb, 1, uint32_t);
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RWHANDLER_WRITE(ioport_simple_writew, 2, uint32_t);
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RWHANDLER_READ(ioport_simple_readw, 2, uint32_t);
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RWHANDLER_WRITE(ioport_simple_writel, 4, uint32_t);
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RWHANDLER_READ(ioport_simple_readl, 4, uint32_t);
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int register_ioport_simple(ReadWriteHandler* handler,
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pio_addr_t start, int length, int size)
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{
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IOPortWriteFunc *write;
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IOPortReadFunc *read;
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int r;
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switch (size) {
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case 1:
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write = ioport_simple_writeb;
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read = ioport_simple_readb;
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break;
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case 2:
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write = ioport_simple_writew;
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read = ioport_simple_readw;
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break;
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default:
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write = ioport_simple_writel;
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read = ioport_simple_readl;
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}
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if (handler->write) {
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r = register_ioport_write(start, length, size, write, handler);
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if (r < 0) {
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return r;
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}
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}
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if (handler->read) {
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r = register_ioport_read(start, length, size, read, handler);
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if (r < 0) {
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return r;
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}
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}
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return 0;
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}
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