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https://gitlab.com/qemu-project/qemu
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2507c12ab0
As stated before, devices can be little, big or native endian. The target endianness is not of their concern, so we need to push things down a level. This patch adds a parameter to cpu_register_io_memory that allows a device to choose its endianness. For now, all devices simply choose native endian, because that's the same behavior as before. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
254 lines
7.3 KiB
C
254 lines
7.3 KiB
C
/*
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* QEMU model of the Xilinx Ethernet Lite MAC.
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*
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* Copyright (c) 2009 Edgar E. Iglesias.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "sysbus.h"
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#include "hw.h"
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#include "net.h"
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#define D(x)
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#define R_TX_BUF0 0
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#define R_TX_LEN0 (0x07f4 / 4)
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#define R_TX_GIE0 (0x07f8 / 4)
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#define R_TX_CTRL0 (0x07fc / 4)
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#define R_TX_BUF1 (0x0800 / 4)
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#define R_TX_LEN1 (0x0ff4 / 4)
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#define R_TX_CTRL1 (0x0ffc / 4)
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#define R_RX_BUF0 (0x1000 / 4)
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#define R_RX_CTRL0 (0x17fc / 4)
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#define R_RX_BUF1 (0x1800 / 4)
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#define R_RX_CTRL1 (0x1ffc / 4)
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#define R_MAX (0x2000 / 4)
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#define GIE_GIE 0x80000000
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#define CTRL_I 0x8
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#define CTRL_P 0x2
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#define CTRL_S 0x1
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struct xlx_ethlite
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{
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SysBusDevice busdev;
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qemu_irq irq;
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NICState *nic;
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NICConf conf;
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uint32_t c_tx_pingpong;
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uint32_t c_rx_pingpong;
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unsigned int txbuf;
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unsigned int rxbuf;
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uint32_t regs[R_MAX];
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};
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static inline void eth_pulse_irq(struct xlx_ethlite *s)
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{
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/* Only the first gie reg is active. */
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if (s->regs[R_TX_GIE0] & GIE_GIE) {
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qemu_irq_pulse(s->irq);
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}
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}
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static uint32_t eth_readl (void *opaque, target_phys_addr_t addr)
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{
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struct xlx_ethlite *s = opaque;
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uint32_t r = 0;
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addr >>= 2;
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switch (addr)
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{
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case R_TX_GIE0:
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case R_TX_LEN0:
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case R_TX_LEN1:
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case R_TX_CTRL1:
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case R_TX_CTRL0:
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case R_RX_CTRL1:
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case R_RX_CTRL0:
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r = s->regs[addr];
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D(qemu_log("%s %x=%x\n", __func__, addr * 4, r));
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break;
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/* Rx packet data is endian fixed at the way into the rx rams. This
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* speeds things up because the ethlite MAC does not have a len
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* register. That means the CPU will issue MMIO reads for the entire
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* 2k rx buffer even for small packets.
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*/
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default:
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r = s->regs[addr];
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break;
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}
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return r;
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}
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static void
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eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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struct xlx_ethlite *s = opaque;
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unsigned int base = 0;
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addr >>= 2;
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switch (addr)
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{
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case R_TX_CTRL0:
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case R_TX_CTRL1:
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if (addr == R_TX_CTRL1)
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base = 0x800 / 4;
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D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
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if ((value & (CTRL_P | CTRL_S)) == CTRL_S) {
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qemu_send_packet(&s->nic->nc,
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(void *) &s->regs[base],
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s->regs[base + R_TX_LEN0]);
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D(qemu_log("eth_tx %d\n", s->regs[base + R_TX_LEN0]));
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if (s->regs[base + R_TX_CTRL0] & CTRL_I)
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eth_pulse_irq(s);
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} else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) {
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memcpy(&s->conf.macaddr.a[0], &s->regs[base], 6);
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if (s->regs[base + R_TX_CTRL0] & CTRL_I)
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eth_pulse_irq(s);
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}
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/* We are fast and get ready pretty much immediately so
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we actually never flip the S nor P bits to one. */
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s->regs[addr] = value & ~(CTRL_P | CTRL_S);
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break;
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/* Keep these native. */
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case R_TX_LEN0:
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case R_TX_LEN1:
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case R_TX_GIE0:
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case R_RX_CTRL0:
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case R_RX_CTRL1:
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D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
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s->regs[addr] = value;
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break;
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/* Packet data, make sure it stays BE. */
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default:
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s->regs[addr] = cpu_to_be32(value);
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break;
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}
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}
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static CPUReadMemoryFunc * const eth_read[] = {
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NULL, NULL, ð_readl,
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};
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static CPUWriteMemoryFunc * const eth_write[] = {
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NULL, NULL, ð_writel,
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};
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static int eth_can_rx(VLANClientState *nc)
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{
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struct xlx_ethlite *s = DO_UPCAST(NICState, nc, nc)->opaque;
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int r;
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r = !(s->regs[R_RX_CTRL0] & CTRL_S);
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return r;
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}
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static ssize_t eth_rx(VLANClientState *nc, const uint8_t *buf, size_t size)
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{
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struct xlx_ethlite *s = DO_UPCAST(NICState, nc, nc)->opaque;
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unsigned int rxbase = s->rxbuf * (0x800 / 4);
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int i;
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/* DA filter. */
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if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6))
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return size;
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if (s->regs[rxbase + R_RX_CTRL0] & CTRL_S) {
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D(qemu_log("ethlite lost packet %x\n", s->regs[R_RX_CTRL0]));
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return -1;
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}
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D(qemu_log("%s %d rxbase=%x\n", __func__, size, rxbase));
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memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size);
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/* Bring it into host endianess. */
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for (i = 0; i < ((size + 3) / 4); i++) {
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uint32_t d = s->regs[rxbase + R_RX_BUF0 + i];
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s->regs[rxbase + R_RX_BUF0 + i] = be32_to_cpu(d);
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}
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s->regs[rxbase + R_RX_CTRL0] |= CTRL_S;
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if (s->regs[rxbase + R_RX_CTRL0] & CTRL_I)
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eth_pulse_irq(s);
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/* If c_rx_pingpong was set flip buffers. */
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s->rxbuf ^= s->c_rx_pingpong;
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return size;
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}
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static void eth_cleanup(VLANClientState *nc)
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{
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struct xlx_ethlite *s = DO_UPCAST(NICState, nc, nc)->opaque;
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s->nic = NULL;
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}
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static NetClientInfo net_xilinx_ethlite_info = {
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.type = NET_CLIENT_TYPE_NIC,
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.size = sizeof(NICState),
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.can_receive = eth_can_rx,
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.receive = eth_rx,
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.cleanup = eth_cleanup,
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};
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static int xilinx_ethlite_init(SysBusDevice *dev)
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{
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struct xlx_ethlite *s = FROM_SYSBUS(typeof (*s), dev);
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int regs;
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sysbus_init_irq(dev, &s->irq);
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s->rxbuf = 0;
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regs = cpu_register_io_memory(eth_read, eth_write, s, DEVICE_NATIVE_ENDIAN);
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sysbus_init_mmio(dev, R_MAX * 4, regs);
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qemu_macaddr_default_if_unset(&s->conf.macaddr);
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s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
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dev->qdev.info->name, dev->qdev.id, s);
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qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
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return 0;
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}
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static SysBusDeviceInfo xilinx_ethlite_info = {
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.init = xilinx_ethlite_init,
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.qdev.name = "xilinx,ethlite",
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.qdev.size = sizeof(struct xlx_ethlite),
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT32("txpingpong", struct xlx_ethlite, c_tx_pingpong, 1),
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DEFINE_PROP_UINT32("rxpingpong", struct xlx_ethlite, c_rx_pingpong, 1),
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DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf),
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DEFINE_PROP_END_OF_LIST(),
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}
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};
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static void xilinx_ethlite_register(void)
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{
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sysbus_register_withprop(&xilinx_ethlite_info);
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}
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device_init(xilinx_ethlite_register)
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