Andrew Jones 6df664f87c Revert "hw/riscv/virt.c: imsics DT: add '#msi-cells'" ... This reverts commit f42cdf2ea5. Linux does not properly handle '#msi-cells=<0>' when searching for MSI controllers for PCI devices which results in the devices being unable to use MSIs. A patch for Linux has been sent[1] but until it, or something like it, is merged and in distro kernels we should stop adding the property. It's harmless to stop adding it since the absence of the property and a value of zero for the property mean the same thing according to the DT binding definition. Link: https://lore.kernel.org/all/20240816124957.130017-2-ajones@ventanamicro.com/ # 1 Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240816160743.220374-5-ajones@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2024-08-19 14:34:49 +10:00
..
boot.c	hw/riscv/boot.c: Support 64-bit address for initrd	2024-06-03 11:12:11 +10:00
Kconfig	kconfig: express dependency of individual boards on libfdt	2024-05-10 15:45:15 +02:00
meson.build	meson: pick libfdt from common_ss when building target-specific files	2024-05-10 15:45:15 +02:00
microchip_pfsoc.c	hw/riscv: use qemu_configure_nic_device()	2024-02-02 16:23:47 +00:00
numa.c	hw/riscv/numa.c: use g_autofree in socket_fdt_write_distance_matrix()	2024-02-09 20:43:14 +10:00
opentitan.c	hw/riscv: opentitan: Fixup local variables shadowing	2023-09-29 10:07:20 +02:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
shakti_c.c	hw/riscv/shakti_c: Check CPU type in machine_run_board_init()	2024-01-05 16:20:15 +01:00
sifive_e.c	riscv: Fix SiFive E CLINT clock frequency	2023-11-22 13:57:19 +10:00
sifive_u.c	target/riscv: support new isa extension detection devicetree properties	2024-02-09 20:43:14 +10:00
spike.c	target/riscv: support new isa extension detection devicetree properties	2024-02-09 20:43:14 +10:00
virt-acpi-build.c	hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART	2024-07-22 20:15:42 -04:00
virt.c	Revert "hw/riscv/virt.c: imsics DT: add '#msi-cells'"	2024-08-19 14:34:49 +10:00