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https://gitlab.com/qemu-project/qemu
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target-alpha: Emulate LL/SC using cmpxchg helpers
Emulating LL/SC with cmpxchg is not correct, since it can suffer from the ABA problem. However, portable parallel code is written assuming only cmpxchg which means that in practice this is a viable alternative. Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
6a73ecf5cf
commit
ed2839166c
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@ -2926,51 +2926,6 @@ void cpu_loop(CPUM68KState *env)
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#endif /* TARGET_M68K */
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#ifdef TARGET_ALPHA
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static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
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{
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target_ulong addr, val, tmp;
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target_siginfo_t info;
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int ret = 0;
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addr = env->lock_addr;
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tmp = env->lock_st_addr;
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env->lock_addr = -1;
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env->lock_st_addr = 0;
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start_exclusive();
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mmap_lock();
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if (addr == tmp) {
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if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
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goto do_sigsegv;
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}
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if (val == env->lock_value) {
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tmp = env->ir[reg];
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if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
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goto do_sigsegv;
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}
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ret = 1;
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}
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}
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env->ir[reg] = ret;
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env->pc += 4;
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mmap_unlock();
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end_exclusive();
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return;
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do_sigsegv:
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mmap_unlock();
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end_exclusive();
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info.si_signo = TARGET_SIGSEGV;
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info.si_errno = 0;
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info.si_code = TARGET_SEGV_MAPERR;
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info._sifields._sigfault._addr = addr;
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queue_signal(env, TARGET_SIGSEGV, QEMU_SI_FAULT, &info);
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}
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void cpu_loop(CPUAlphaState *env)
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{
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CPUState *cs = CPU(alpha_env_get_cpu(env));
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@ -3145,10 +3100,6 @@ void cpu_loop(CPUAlphaState *env)
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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}
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break;
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case EXCP_STL_C:
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case EXCP_STQ_C:
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do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
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break;
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case EXCP_INTERRUPT:
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/* Just indicate that signals should be handled asap. */
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break;
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@ -230,7 +230,6 @@ struct CPUAlphaState {
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uint64_t pc;
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uint64_t unique;
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uint64_t lock_addr;
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uint64_t lock_st_addr;
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uint64_t lock_value;
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/* The FPCR, and disassembled portions thereof. */
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@ -346,9 +345,6 @@ enum {
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EXCP_ARITH,
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EXCP_FEN,
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EXCP_CALL_PAL,
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/* For Usermode emulation. */
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EXCP_STL_C,
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EXCP_STQ_C,
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};
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/* Alpha-specific interrupt pending bits. */
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@ -306,12 +306,6 @@ void alpha_cpu_do_interrupt(CPUState *cs)
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case EXCP_CALL_PAL:
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name = "call_pal";
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break;
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case EXCP_STL_C:
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name = "stl_c";
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break;
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case EXCP_STQ_C:
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name = "stq_c";
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break;
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}
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qemu_log("INT %6d: %s(%#x) pc=%016" PRIx64 " sp=%016" PRIx64 "\n",
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++count, name, env->error_code, env->pc, env->ir[IR_SP]);
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@ -45,8 +45,6 @@ static VMStateField vmstate_env_fields[] = {
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VMSTATE_UINTTL(unique, CPUAlphaState),
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VMSTATE_UINTTL(lock_addr, CPUAlphaState),
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VMSTATE_UINTTL(lock_value, CPUAlphaState),
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/* Note that lock_st_addr is not saved; it is a temporary
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used during the execution of the st[lq]_c insns. */
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VMSTATE_UINT8(ps, CPUAlphaState),
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VMSTATE_UINT8(intr_flag, CPUAlphaState),
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@ -99,7 +99,6 @@ static TCGv cpu_std_ir[31];
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static TCGv cpu_fir[31];
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static TCGv cpu_pc;
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static TCGv cpu_lock_addr;
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static TCGv cpu_lock_st_addr;
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static TCGv cpu_lock_value;
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#ifndef CONFIG_USER_ONLY
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@ -116,7 +115,6 @@ void alpha_translate_init(void)
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static const GlobalVar vars[] = {
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DEF_VAR(pc),
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DEF_VAR(lock_addr),
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DEF_VAR(lock_st_addr),
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DEF_VAR(lock_value),
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};
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@ -198,6 +196,23 @@ static TCGv dest_sink(DisasContext *ctx)
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return ctx->sink;
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}
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static void free_context_temps(DisasContext *ctx)
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{
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if (!TCGV_IS_UNUSED_I64(ctx->sink)) {
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tcg_gen_discard_i64(ctx->sink);
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tcg_temp_free(ctx->sink);
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TCGV_UNUSED_I64(ctx->sink);
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}
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if (!TCGV_IS_UNUSED_I64(ctx->zero)) {
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tcg_temp_free(ctx->zero);
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TCGV_UNUSED_I64(ctx->zero);
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}
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if (!TCGV_IS_UNUSED_I64(ctx->lit)) {
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tcg_temp_free(ctx->lit);
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TCGV_UNUSED_I64(ctx->lit);
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}
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}
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static TCGv load_gpr(DisasContext *ctx, unsigned reg)
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{
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if (likely(reg < 31)) {
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@ -395,56 +410,37 @@ static ExitStatus gen_store_conditional(DisasContext *ctx, int ra, int rb,
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int32_t disp16, int mem_idx,
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TCGMemOp op)
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{
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TCGv addr;
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if (ra == 31) {
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/* ??? Don't bother storing anything. The user can't tell
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the difference, since the zero register always reads zero. */
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return NO_EXIT;
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}
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#if defined(CONFIG_USER_ONLY)
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addr = cpu_lock_st_addr;
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#else
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addr = tcg_temp_local_new();
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#endif
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TCGLabel *lab_fail, *lab_done;
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TCGv addr, val;
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addr = tcg_temp_new_i64();
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tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
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free_context_temps(ctx);
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#if defined(CONFIG_USER_ONLY)
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/* ??? This is handled via a complicated version of compare-and-swap
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in the cpu_loop. Hopefully one day we'll have a real CAS opcode
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in TCG so that this isn't necessary. */
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return gen_excp(ctx, (op & MO_SIZE) == MO_64 ? EXCP_STQ_C : EXCP_STL_C, ra);
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#else
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/* ??? In system mode we are never multi-threaded, so CAS can be
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implemented via a non-atomic load-compare-store sequence. */
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{
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TCGLabel *lab_fail, *lab_done;
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TCGv val;
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lab_fail = gen_new_label();
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lab_done = gen_new_label();
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tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_lock_addr, lab_fail);
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tcg_temp_free_i64(addr);
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lab_fail = gen_new_label();
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lab_done = gen_new_label();
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tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_lock_addr, lab_fail);
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val = tcg_temp_new_i64();
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tcg_gen_atomic_cmpxchg_i64(val, cpu_lock_addr, cpu_lock_value,
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load_gpr(ctx, ra), mem_idx, op);
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free_context_temps(ctx);
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val = tcg_temp_new();
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tcg_gen_qemu_ld_i64(val, addr, mem_idx, op);
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tcg_gen_brcond_i64(TCG_COND_NE, val, cpu_lock_value, lab_fail);
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tcg_gen_qemu_st_i64(ctx->ir[ra], addr, mem_idx, op);
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tcg_gen_movi_i64(ctx->ir[ra], 1);
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tcg_gen_br(lab_done);
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gen_set_label(lab_fail);
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tcg_gen_movi_i64(ctx->ir[ra], 0);
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gen_set_label(lab_done);
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tcg_gen_movi_i64(cpu_lock_addr, -1);
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tcg_temp_free(addr);
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return NO_EXIT;
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if (ra != 31) {
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tcg_gen_setcond_i64(TCG_COND_EQ, ctx->ir[ra], val, cpu_lock_value);
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}
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#endif
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tcg_temp_free_i64(val);
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tcg_gen_br(lab_done);
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gen_set_label(lab_fail);
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if (ra != 31) {
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tcg_gen_movi_i64(ctx->ir[ra], 0);
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}
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gen_set_label(lab_done);
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tcg_gen_movi_i64(cpu_lock_addr, -1);
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return NO_EXIT;
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}
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static bool in_superpage(DisasContext *ctx, int64_t addr)
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@ -2914,6 +2910,10 @@ void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb)
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/* Similarly for flush-to-zero. */
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ctx.tb_ftz = -1;
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TCGV_UNUSED_I64(ctx.zero);
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TCGV_UNUSED_I64(ctx.sink);
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TCGV_UNUSED_I64(ctx.lit);
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num_insns = 0;
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max_insns = tb->cflags & CF_COUNT_MASK;
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if (max_insns == 0) {
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@ -2948,23 +2948,9 @@ void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb)
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}
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insn = cpu_ldl_code(env, ctx.pc);
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TCGV_UNUSED_I64(ctx.zero);
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TCGV_UNUSED_I64(ctx.sink);
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TCGV_UNUSED_I64(ctx.lit);
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ctx.pc += 4;
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ret = translate_one(ctxp, insn);
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if (!TCGV_IS_UNUSED_I64(ctx.sink)) {
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tcg_gen_discard_i64(ctx.sink);
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tcg_temp_free(ctx.sink);
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}
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if (!TCGV_IS_UNUSED_I64(ctx.zero)) {
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tcg_temp_free(ctx.zero);
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}
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if (!TCGV_IS_UNUSED_I64(ctx.lit)) {
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tcg_temp_free(ctx.lit);
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}
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free_context_temps(ctxp);
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/* If we reach a page boundary, are single stepping,
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or exhaust instruction count, stop generation. */
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