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target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words)
Introduce the PROT3W opcode (Parallel Rotate 3 Words). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-25-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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@ -54,6 +54,7 @@ PEXTUW 011100 ..... ..... ..... 10010 101000 @rs_rt_rd
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PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd
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PAND 011100 ..... ..... ..... 10010 001001 @rs_rt_rd
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PXOR 011100 ..... ..... ..... 10011 001001 @rs_rt_rd
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PROT3W 011100 00000 ..... ..... 11111 001001 @rt_rd
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# MMI3
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@ -593,3 +593,31 @@ static bool trans_PCPYUD(DisasContext *s, arg_rtype *a)
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return true;
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}
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/* Parallel Rotate 3 Words Left */
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static bool trans_PROT3W(DisasContext *ctx, arg_rtype *a)
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{
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TCGv_i64 ax;
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if (a->rd == 0) {
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/* nop */
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return true;
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}
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if (a->rt == 0) {
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tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
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tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
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return true;
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}
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ax = tcg_temp_new_i64();
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tcg_gen_mov_i64(ax, cpu_gpr_hi[a->rt]);
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tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], ax, cpu_gpr[a->rt], 0, 32);
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tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], ax, 0, 32);
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tcg_gen_rotri_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], 32);
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tcg_temp_free(ax);
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return true;
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}
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