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target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word)
Introduce the PPACW opcode (Parallel Pack to Word). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-22-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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@ -38,6 +38,7 @@ PCGTH 011100 ..... ..... ..... 00110 001000 @rs_rt_rd
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PSUBB 011100 ..... ..... ..... 01001 001000 @rs_rt_rd
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PCGTB 011100 ..... ..... ..... 01010 001000 @rs_rt_rd
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PEXTLW 011100 ..... ..... ..... 10010 001000 @rs_rt_rd
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PPACW 011100 ..... ..... ..... 10011 001000 @rs_rt_rd
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PEXTLH 011100 ..... ..... ..... 10110 001000 @rs_rt_rd
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PEXTLB 011100 ..... ..... ..... 11010 001000 @rs_rt_rd
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@ -374,6 +374,36 @@ static bool trans_PCEQW(DisasContext *ctx, arg_rtype *a)
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* PEXTLW rd, rs, rt Parallel Extend Lower from Word
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*/
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/* Parallel Pack to Word */
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static bool trans_PPACW(DisasContext *ctx, arg_rtype *a)
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{
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TCGv_i64 a0, b0, t0;
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if (a->rd == 0) {
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/* nop */
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return true;
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}
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a0 = tcg_temp_new_i64();
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b0 = tcg_temp_new_i64();
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t0 = tcg_temp_new_i64();
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gen_load_gpr(a0, a->rs);
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gen_load_gpr(b0, a->rt);
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gen_load_gpr_hi(t0, a->rt); /* b1 */
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tcg_gen_deposit_i64(cpu_gpr[a->rd], b0, t0, 32, 32);
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gen_load_gpr_hi(t0, a->rs); /* a1 */
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tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], a0, t0, 32, 32);
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tcg_temp_free(t0);
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tcg_temp_free(b0);
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tcg_temp_free(a0);
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return true;
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}
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static void gen_pextw(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 a, TCGv_i64 b)
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{
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tcg_gen_deposit_i64(dl, b, a, 32, 32);
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