mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-11-05 20:35:44 +00:00
target-alpha: Move fpcr helpers from op_helper.c to helper.c.
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
parent
4a58aedff4
commit
a44a27775a
4 changed files with 17 additions and 17 deletions
|
@ -159,9 +159,19 @@ void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val)
|
|||
env->fpcr_undz = (val & FPCR_UNDZ) != 0;
|
||||
}
|
||||
|
||||
uint64_t helper_load_fpcr(CPUAlphaState *env)
|
||||
{
|
||||
return cpu_alpha_load_fpcr(env);
|
||||
}
|
||||
|
||||
void helper_store_fpcr(CPUAlphaState *env, uint64_t val)
|
||||
{
|
||||
cpu_alpha_store_fpcr(env, val);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_USER_ONLY)
|
||||
int cpu_alpha_handle_mmu_fault (CPUAlphaState *env, target_ulong address, int rw,
|
||||
int mmu_idx)
|
||||
int cpu_alpha_handle_mmu_fault(CPUAlphaState *env, target_ulong address,
|
||||
int rw, int mmu_idx)
|
||||
{
|
||||
env->exception_index = EXCP_MMFAULT;
|
||||
env->trap_arg0 = address;
|
||||
|
|
|
@ -34,8 +34,8 @@ DEF_HELPER_FLAGS_1(pkwb, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64)
|
|||
DEF_HELPER_FLAGS_1(unpkbl, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64)
|
||||
DEF_HELPER_FLAGS_1(unpkbw, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64)
|
||||
|
||||
DEF_HELPER_FLAGS_0(load_fpcr, TCG_CALL_CONST | TCG_CALL_PURE, i64)
|
||||
DEF_HELPER_FLAGS_1(store_fpcr, TCG_CALL_CONST, void, i64)
|
||||
DEF_HELPER_FLAGS_1(load_fpcr, TCG_CALL_CONST | TCG_CALL_PURE, i64, env)
|
||||
DEF_HELPER_FLAGS_2(store_fpcr, TCG_CALL_CONST, void, env, i64)
|
||||
|
||||
DEF_HELPER_FLAGS_1(f_to_memory, TCG_CALL_CONST | TCG_CALL_PURE, i32, i64)
|
||||
DEF_HELPER_FLAGS_1(memory_to_f, TCG_CALL_CONST | TCG_CALL_PURE, i64, i32)
|
||||
|
|
|
@ -43,16 +43,6 @@ uint64_t helper_load_pcc (void)
|
|||
#endif
|
||||
}
|
||||
|
||||
uint64_t helper_load_fpcr (void)
|
||||
{
|
||||
return cpu_alpha_load_fpcr (env);
|
||||
}
|
||||
|
||||
void helper_store_fpcr (uint64_t val)
|
||||
{
|
||||
cpu_alpha_store_fpcr (env, val);
|
||||
}
|
||||
|
||||
uint64_t helper_addqv (uint64_t op1, uint64_t op2)
|
||||
{
|
||||
uint64_t tmp = op1;
|
||||
|
|
|
@ -2678,17 +2678,17 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
|
|||
case 0x024:
|
||||
/* MT_FPCR */
|
||||
if (likely(ra != 31))
|
||||
gen_helper_store_fpcr(cpu_fir[ra]);
|
||||
gen_helper_store_fpcr(cpu_env, cpu_fir[ra]);
|
||||
else {
|
||||
TCGv tmp = tcg_const_i64(0);
|
||||
gen_helper_store_fpcr(tmp);
|
||||
gen_helper_store_fpcr(cpu_env, tmp);
|
||||
tcg_temp_free(tmp);
|
||||
}
|
||||
break;
|
||||
case 0x025:
|
||||
/* MF_FPCR */
|
||||
if (likely(ra != 31))
|
||||
gen_helper_load_fpcr(cpu_fir[ra]);
|
||||
gen_helper_load_fpcr(cpu_fir[ra], cpu_env);
|
||||
break;
|
||||
case 0x02A:
|
||||
/* FCMOVEQ */
|
||||
|
|
Loading…
Reference in a new issue