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target/loongarch: Sign extend results in VA32 mode

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In VA32 mode, BL, JIRL and PC* instructions should sign-extend the low
32 bit result to 64 bits.

Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230822032724.1353391-7-gaosong@loongson.cn>
Message-Id: <20230822071959.35620-1-philmd@linaro.org>
This commit is contained in:
Jiajie Chen 2023-08-22 09:19:50 +02:00 committed by Song Gao
parent 7033c0e6dd
commit 6496269d7e
No known key found for this signature in database
GPG key ID: 40A2FFF239263EDF
1 changed files with 3 additions and 0 deletions
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3
target/loongarch/translate.c
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@ -238,6 +238,9 @@ static TCGv make_address_i(DisasContext *ctx, TCGv base, target_long ofs)
static uint64_t make_address_pc(DisasContext *ctx, uint64_t addr)
{
if (ctx->va32) {
addr = (int32_t)addr;
}
return addr;
}