system/qemu
system/qemu
1
0
Fork 0
mirror of https://gitlab.com/qemu-project/qemu synced 2024-10-14 15:02:54 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/loongarch: Truncate high 32 bits of address in VA32 mode

Browse source 
When running in VA32 mode(!LA64 or VA32L[1-3] matching PLV), virtual
address is truncated to 32 bits before address mapping.

Signed-off-by: Jiajie Chen <c@jia.je>
Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn>
Message-Id: <20230822071405.35386-10-philmd@linaro.org>
This commit is contained in:
Jiajie Chen 2023-08-22 09:13:55 +02:00 committed by Song Gao
parent 2f6478ffad
commit 7033c0e6dd
No known key found for this signature in database
GPG key ID: 40A2FFF239263EDF
2 changed files with 20 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
target/loongarch/cpu.h
View file

@ -445,7 +445,11 @@ static inline bool is_va32(CPULoongArchState *env)
static inline void set_pc(CPULoongArchState *env, uint64_t value)
{
env->pc = value;
if (is_va32(env)) {
env->pc = (uint32_t)value;
} else {
env->pc = value;
}
}
/*

16
target/loongarch/translate.c
View file

@ -86,6 +86,10 @@ void generate_exception(DisasContext *ctx, int excp)
static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
{
if (ctx->va32) {
dest = (uint32_t) dest;
}
if (translator_use_goto_tb(&ctx->base, dest)) {
tcg_gen_goto_tb(n);
tcg_gen_movi_tl(cpu_pc, dest);
@ -212,11 +216,17 @@ static TCGv make_address_x(DisasContext *ctx, TCGv base, TCGv addend)
{
TCGv temp = NULL;
if (addend) {
if (addend || ctx->va32) {
temp = tcg_temp_new();
}
if (addend) {
tcg_gen_add_tl(temp, base, addend);
base = temp;
}
if (ctx->va32) {
tcg_gen_ext32u_tl(temp, base);
base = temp;
}
return base;
}
@ -262,6 +272,10 @@ static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
}
ctx->base.pc_next += 4;
if (ctx->va32) {
ctx->base.pc_next = (uint32_t)ctx->base.pc_next;
}
}
static void loongarch_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)