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target-mips: add compact and CP1 branches
Introduce MIPS32R6 Compact Branch instructions which do not have delay slot - they have forbidden slot instead. However, current implementation does not support forbidden slot yet. Add also BC1EQZ and BC1NEZ instructions. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
parent
15eacb9b52
commit
31837be3ee
67
disas/mips.c
67
disas/mips.c
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@ -1250,6 +1250,34 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"dalign", "d,v,t", 0x7c000224, 0xfc00063f, WR_d|RD_s|RD_t, 0, I64R6},
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{"bitswap", "d,w", 0x7c000020, 0xffe007ff, WR_d|RD_t, 0, I32R6},
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{"dbitswap","d,w", 0x7c000024, 0xffe007ff, WR_d|RD_t, 0, I64R6},
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{"balc", "+p", 0xe8000000, 0xfc000000, UBD|WR_31, 0, I32R6},
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{"bc", "+p", 0xc8000000, 0xfc000000, UBD|WR_31, 0, I32R6},
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{"jic", "t,o", 0xd8000000, 0xffe00000, UBD|RD_t, 0, I32R6},
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{"beqzc", "s,+p", 0xd8000000, 0xfc000000, CBD|RD_s, 0, I32R6},
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{"jialc", "t,o", 0xf8000000, 0xffe00000, UBD|RD_t, 0, I32R6},
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{"bnezc", "s,+p", 0xf8000000, 0xfc000000, CBD|RD_s, 0, I32R6},
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{"beqzalc", "s,t,p", 0x20000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6},
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{"bovc", "s,t,p", 0x20000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
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{"beqc", "s,t,p", 0x20000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
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{"bnezalc", "s,t,p", 0x60000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6},
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{"bnvc", "s,t,p", 0x60000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
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{"bnec", "s,t,p", 0x60000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
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{"blezc", "s,t,p", 0x58000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6},
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{"bgezc", "s,t,p", 0x58000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
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{"bgec", "s,t,p", 0x58000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
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{"bgtzc", "s,t,p", 0x5c000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6},
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{"bltzc", "s,t,p", 0x5c000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
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{"bltc", "s,t,p", 0x5c000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
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{"blezalc", "s,t,p", 0x18000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6},
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{"bgezalc", "s,t,p", 0x18000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
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{"bgeuc", "s,t,p", 0x18000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
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{"bgtzalc", "s,t,p", 0x1c000000, 0xffe00000, CBD|RD_s|RD_t, 0, I32R6},
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{"bltzalc", "s,t,p", 0x1c000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
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{"bltuc", "s,t,p", 0x1c000000, 0xfc000000, CBD|RD_s|RD_t, 0, I32R6},
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{"bc1eqz", "T,p", 0x45200000, 0xffe00000, CBD|RD_T|FP_S|FP_D, 0, I32R6},
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{"bc1nez", "T,p", 0x45a00000, 0xffe00000, CBD|RD_T|FP_S|FP_D, 0, I32R6},
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{"bc2eqz", "E,p", 0x49200000, 0xffe00000, CBD|RD_C2, 0, I32R6},
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{"bc2nez", "E,p", 0x49a00000, 0xffe00000, CBD|RD_C2, 0, I32R6},
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{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4|I32|G3 },
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{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4|I33 },
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{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
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@ -3616,6 +3644,24 @@ print_insn_args (const char *d,
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(*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
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break;
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case 'o':
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delta = (l >> OP_SH_DELTA_R6) & OP_MASK_DELTA_R6;
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if (delta & 0x8000) {
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delta |= ~0xffff;
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}
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(*info->fprintf_func) (info->stream, "%d", delta);
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break;
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case 'p':
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/* Sign extend the displacement with 26 bits. */
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delta = (l >> OP_SH_DELTA) & OP_MASK_TARGET;
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if (delta & 0x2000000) {
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delta |= ~0x3FFFFFF;
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}
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info->target = (delta << 2) + pc + INSNLEN;
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(*info->print_address_func) (info->target, info);
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break;
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case 't': /* Coprocessor 0 reg name */
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(*info->fprintf_func) (info->stream, "%s",
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mips_cp0_names[(l >> OP_SH_RT) &
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@ -3767,9 +3813,7 @@ print_insn_args (const char *d,
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case 'j': /* Same as i, but sign-extended. */
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case 'o':
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delta = (opp->membership == I32R6) ?
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(l >> OP_SH_DELTA_R6) & OP_MASK_DELTA_R6 :
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(l >> OP_SH_DELTA) & OP_MASK_DELTA;
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delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
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if (delta & 0x8000)
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delta |= ~0xffff;
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@ -4096,6 +4140,23 @@ print_insn_mips (bfd_vma memaddr,
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&& strcmp (op->name, "jalx"))
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continue;
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if (strcmp(op->name, "bovc") == 0
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|| strcmp(op->name, "bnvc") == 0) {
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if (((word >> OP_SH_RS) & OP_MASK_RS) <
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((word >> OP_SH_RT) & OP_MASK_RT)) {
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continue;
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}
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}
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if (strcmp(op->name, "bgezc") == 0
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|| strcmp(op->name, "bltzc") == 0
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|| strcmp(op->name, "bgezalc") == 0
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|| strcmp(op->name, "bltzalc") == 0) {
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if (((word >> OP_SH_RS) & OP_MASK_RS) !=
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((word >> OP_SH_RT) & OP_MASK_RT)) {
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continue;
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}
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}
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/* Figure out instruction type and branch delay information. */
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if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
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{
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@ -111,6 +111,31 @@ enum {
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OPC_SWC2 = (0x3A << 26),
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OPC_SDC1 = (0x3D << 26),
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OPC_SDC2 = (0x3E << 26),
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/* Compact Branches */
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OPC_BLEZALC = (0x06 << 26),
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OPC_BGEZALC = (0x06 << 26),
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OPC_BGEUC = (0x06 << 26),
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OPC_BGTZALC = (0x07 << 26),
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OPC_BLTZALC = (0x07 << 26),
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OPC_BLTUC = (0x07 << 26),
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OPC_BOVC = (0x08 << 26),
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OPC_BEQZALC = (0x08 << 26),
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OPC_BEQC = (0x08 << 26),
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OPC_BLEZC = (0x16 << 26),
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OPC_BGEZC = (0x16 << 26),
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OPC_BGEC = (0x16 << 26),
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OPC_BGTZC = (0x17 << 26),
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OPC_BLTZC = (0x17 << 26),
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OPC_BLTC = (0x17 << 26),
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OPC_BNVC = (0x18 << 26),
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OPC_BNEZALC = (0x18 << 26),
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OPC_BNEC = (0x18 << 26),
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OPC_BC = (0x32 << 26),
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OPC_BEQZC = (0x36 << 26),
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OPC_JIC = (0x36 << 26),
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OPC_BALC = (0x3A << 26),
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OPC_BNEZC = (0x3E << 26),
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OPC_JIALC = (0x3E << 26),
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/* MDMX ASE specific */
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OPC_MDMX = (0x1E << 26),
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/* Cache and prefetch */
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@ -897,6 +922,8 @@ enum {
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OPC_W_FMT = (FMT_W << 21) | OPC_CP1,
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OPC_L_FMT = (FMT_L << 21) | OPC_CP1,
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OPC_PS_FMT = (FMT_PS << 21) | OPC_CP1,
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OPC_BC1EQZ = (0x09 << 21) | OPC_CP1,
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OPC_BC1NEZ = (0x0D << 21) | OPC_CP1,
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};
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#define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
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@ -931,6 +958,8 @@ enum {
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OPC_CTC2 = (0x06 << 21) | OPC_CP2,
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OPC_MTHC2 = (0x07 << 21) | OPC_CP2,
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OPC_BC2 = (0x08 << 21) | OPC_CP2,
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OPC_BC2EQZ = (0x09 << 21) | OPC_CP2,
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OPC_BC2NEZ = (0x0D << 21) | OPC_CP2,
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};
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#define MASK_LMI(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)) | (op & 0x1F))
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@ -1395,6 +1424,20 @@ static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0, TCGv
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#endif
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}
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/* Addresses computation (translation time) */
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static target_long addr_add(DisasContext *ctx, target_long base,
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target_long offset)
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{
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target_long sum = base + offset;
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#if defined(TARGET_MIPS64)
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if (ctx->hflags & MIPS_HFLAG_AWRAP) {
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sum = (int32_t)sum;
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}
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#endif
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return sum;
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}
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static inline void check_cp0_enabled(DisasContext *ctx)
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{
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if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0)))
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@ -7433,6 +7476,55 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
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tcg_temp_free_i32(t0);
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}
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/* R6 CP1 Branches */
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static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op,
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int32_t ft, int32_t offset)
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{
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target_ulong btarget;
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const char *opn = "cp1 cond branch";
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TCGv_i64 t0 = tcg_temp_new_i64();
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if (ctx->hflags & MIPS_HFLAG_BMASK) {
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#ifdef MIPS_DEBUG_DISAS
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LOG_DISAS("Branch in delay slot at PC 0x" TARGET_FMT_lx "\n", ctx->pc);
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#endif
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generate_exception(ctx, EXCP_RI);
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goto out;
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}
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gen_load_fpr64(ctx, t0, ft);
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tcg_gen_andi_i64(t0, t0, 1);
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btarget = addr_add(ctx, ctx->pc + 4, offset);
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switch (op) {
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case OPC_BC1EQZ:
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tcg_gen_xori_i64(t0, t0, 1);
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opn = "bc1eqz";
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ctx->hflags |= MIPS_HFLAG_BC;
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break;
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case OPC_BC1NEZ:
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/* t0 already set */
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opn = "bc1nez";
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ctx->hflags |= MIPS_HFLAG_BC;
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break;
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default:
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MIPS_INVAL(opn);
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generate_exception(ctx, EXCP_RI);
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goto out;
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}
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tcg_gen_trunc_i64_tl(bcond, t0);
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(void)opn; /* avoid a compiler warning */
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MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx, opn,
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ctx->hflags, btarget);
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ctx->btarget = btarget;
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out:
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tcg_temp_free_i64(t0);
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}
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/* Coprocessor 1 (FPU) */
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#define FOP(func, fmt) (((fmt) << 21) | (func))
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@ -9438,7 +9530,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd)
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tcg_temp_free(t0);
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}
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static void handle_delay_slot(DisasContext *ctx, int insn_bytes)
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static void gen_branch(DisasContext *ctx, int insn_bytes)
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{
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if (ctx->hflags & MIPS_HFLAG_BMASK) {
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int proc_hflags = ctx->hflags & MIPS_HFLAG_BMASK;
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@ -14757,6 +14849,242 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
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/* End MIPSDSP functions. */
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/* Compact Branches */
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static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
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int rs, int rt, int32_t offset)
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{
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int bcond_compute = 0;
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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if (ctx->hflags & MIPS_HFLAG_BMASK) {
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#ifdef MIPS_DEBUG_DISAS
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LOG_DISAS("Branch in delay slot at PC 0x" TARGET_FMT_lx "\n", ctx->pc);
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#endif
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generate_exception(ctx, EXCP_RI);
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goto out;
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}
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/* Load needed operands and calculate btarget */
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switch (opc) {
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/* compact branch */
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case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC */
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case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */
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gen_load_gpr(t0, rs);
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gen_load_gpr(t1, rt);
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bcond_compute = 1;
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ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
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if (rs <= rt && rs == 0) {
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/* OPC_BEQZALC, OPC_BNEZALC */
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tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 4);
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}
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break;
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case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */
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case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC */
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gen_load_gpr(t0, rs);
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gen_load_gpr(t1, rt);
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bcond_compute = 1;
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ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
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break;
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case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */
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case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */
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if (rs == 0 || rs == rt) {
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/* OPC_BLEZALC, OPC_BGEZALC */
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/* OPC_BGTZALC, OPC_BLTZALC */
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tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 4);
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}
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gen_load_gpr(t0, rs);
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gen_load_gpr(t1, rt);
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bcond_compute = 1;
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ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
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break;
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case OPC_BC:
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case OPC_BALC:
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ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
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break;
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case OPC_BEQZC:
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case OPC_BNEZC:
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if (rs != 0) {
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/* OPC_BEQZC, OPC_BNEZC */
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gen_load_gpr(t0, rs);
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bcond_compute = 1;
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ctx->btarget = addr_add(ctx, ctx->pc + 4, offset);
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} else {
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/* OPC_JIC, OPC_JIALC */
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TCGv tbase = tcg_temp_new();
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TCGv toffset = tcg_temp_new();
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gen_load_gpr(tbase, rt);
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tcg_gen_movi_tl(toffset, offset);
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gen_op_addr_add(ctx, btarget, tbase, toffset);
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tcg_temp_free(tbase);
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tcg_temp_free(toffset);
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}
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break;
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default:
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MIPS_INVAL("Compact branch/jump");
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generate_exception(ctx, EXCP_RI);
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goto out;
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}
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if (bcond_compute == 0) {
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/* Uncoditional compact branch */
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switch (opc) {
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case OPC_JIALC:
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tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 4);
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/* Fallthrough */
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case OPC_JIC:
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ctx->hflags |= MIPS_HFLAG_BR;
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break;
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case OPC_BALC:
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tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 4);
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/* Fallthrough */
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case OPC_BC:
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ctx->hflags |= MIPS_HFLAG_B;
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break;
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default:
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MIPS_INVAL("Compact branch/jump");
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generate_exception(ctx, EXCP_RI);
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goto out;
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}
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/* Generating branch here as compact branches don't have delay slot */
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gen_branch(ctx, 4);
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} else {
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/* Conditional compact branch */
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int l1 = gen_new_label();
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save_cpu_state(ctx, 0);
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switch (opc) {
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case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */
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if (rs == 0 && rt != 0) {
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/* OPC_BLEZALC */
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tcg_gen_brcondi_tl(TCG_COND_LE, t1, 0, l1);
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} else if (rs != 0 && rt != 0 && rs == rt) {
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/* OPC_BGEZALC */
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tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
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} else {
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/* OPC_BGEUC */
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tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
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}
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break;
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case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */
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if (rs == 0 && rt != 0) {
|
||||
/* OPC_BGTZALC */
|
||||
tcg_gen_brcondi_tl(TCG_COND_GT, t1, 0, l1);
|
||||
} else if (rs != 0 && rt != 0 && rs == rt) {
|
||||
/* OPC_BLTZALC */
|
||||
tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
|
||||
} else {
|
||||
/* OPC_BLTUC */
|
||||
tcg_gen_brcond_tl(TCG_COND_LTU, t0, t1, l1);
|
||||
}
|
||||
break;
|
||||
case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */
|
||||
if (rs == 0 && rt != 0) {
|
||||
/* OPC_BLEZC */
|
||||
tcg_gen_brcondi_tl(TCG_COND_LE, t1, 0, l1);
|
||||
} else if (rs != 0 && rt != 0 && rs == rt) {
|
||||
/* OPC_BGEZC */
|
||||
tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
|
||||
} else {
|
||||
/* OPC_BGEC */
|
||||
tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
|
||||
}
|
||||
break;
|
||||
case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC */
|
||||
if (rs == 0 && rt != 0) {
|
||||
/* OPC_BGTZC */
|
||||
tcg_gen_brcondi_tl(TCG_COND_GT, t1, 0, l1);
|
||||
} else if (rs != 0 && rt != 0 && rs == rt) {
|
||||
/* OPC_BLTZC */
|
||||
tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
|
||||
} else {
|
||||
/* OPC_BLTC */
|
||||
tcg_gen_brcond_tl(TCG_COND_LT, t0, t1, l1);
|
||||
}
|
||||
break;
|
||||
case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC */
|
||||
case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */
|
||||
if (rs >= rt) {
|
||||
/* OPC_BOVC, OPC_BNVC */
|
||||
TCGv t2 = tcg_temp_new();
|
||||
TCGv t3 = tcg_temp_new();
|
||||
TCGv t4 = tcg_temp_new();
|
||||
TCGv input_overflow = tcg_temp_new();
|
||||
|
||||
gen_load_gpr(t0, rs);
|
||||
gen_load_gpr(t1, rt);
|
||||
tcg_gen_ext32s_tl(t2, t0);
|
||||
tcg_gen_setcond_tl(TCG_COND_NE, input_overflow, t2, t0);
|
||||
tcg_gen_ext32s_tl(t3, t1);
|
||||
tcg_gen_setcond_tl(TCG_COND_NE, t4, t3, t1);
|
||||
tcg_gen_or_tl(input_overflow, input_overflow, t4);
|
||||
|
||||
tcg_gen_add_tl(t4, t2, t3);
|
||||
tcg_gen_ext32s_tl(t4, t4);
|
||||
tcg_gen_xor_tl(t2, t2, t3);
|
||||
tcg_gen_xor_tl(t3, t4, t3);
|
||||
tcg_gen_andc_tl(t2, t3, t2);
|
||||
tcg_gen_setcondi_tl(TCG_COND_LT, t4, t2, 0);
|
||||
tcg_gen_or_tl(t4, t4, input_overflow);
|
||||
if (opc == OPC_BOVC) {
|
||||
/* OPC_BOVC */
|
||||
tcg_gen_brcondi_tl(TCG_COND_NE, t4, 0, l1);
|
||||
} else {
|
||||
/* OPC_BNVC */
|
||||
tcg_gen_brcondi_tl(TCG_COND_EQ, t4, 0, l1);
|
||||
}
|
||||
tcg_temp_free(input_overflow);
|
||||
tcg_temp_free(t4);
|
||||
tcg_temp_free(t3);
|
||||
tcg_temp_free(t2);
|
||||
} else if (rs < rt && rs == 0) {
|
||||
/* OPC_BEQZALC, OPC_BNEZALC */
|
||||
if (opc == OPC_BEQZALC) {
|
||||
/* OPC_BEQZALC */
|
||||
tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
|
||||
} else {
|
||||
/* OPC_BNEZALC */
|
||||
tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
|
||||
}
|
||||
} else {
|
||||
/* OPC_BEQC, OPC_BNEC */
|
||||
if (opc == OPC_BEQC) {
|
||||
/* OPC_BEQC */
|
||||
tcg_gen_brcond_tl(TCG_COND_EQ, t0, t1, l1);
|
||||
} else {
|
||||
/* OPC_BNEC */
|
||||
tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l1);
|
||||
}
|
||||
}
|
||||
break;
|
||||
case OPC_BEQZC:
|
||||
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
||||
break;
|
||||
case OPC_BNEZC:
|
||||
tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
|
||||
break;
|
||||
default:
|
||||
MIPS_INVAL("Compact conditional branch/jump");
|
||||
generate_exception(ctx, EXCP_RI);
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Generating branch here as compact branches don't have delay slot */
|
||||
/* TODO: implement forbidden slot */
|
||||
gen_goto_tb(ctx, 1, ctx->pc + 4);
|
||||
gen_set_label(l1);
|
||||
gen_goto_tb(ctx, 0, ctx->btarget);
|
||||
MIPS_DEBUG("Compact conditional branch");
|
||||
ctx->bstate = BS_BRANCH;
|
||||
}
|
||||
|
||||
out:
|
||||
tcg_temp_free(t0);
|
||||
tcg_temp_free(t1);
|
||||
}
|
||||
|
||||
static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
|
||||
{
|
||||
int rs, rt, rd, sa;
|
||||
|
@ -16063,7 +16391,16 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
|
|||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_ADDI: /* Arithmetic with immediate opcode */
|
||||
case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC, OPC_ADDI */
|
||||
if (ctx->insn_flags & ISA_MIPS32R6) {
|
||||
/* OPC_BOVC, OPC_BEQZALC, OPC_BEQC */
|
||||
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
|
||||
} else {
|
||||
/* OPC_ADDI */
|
||||
/* Arithmetic with immediate opcode */
|
||||
gen_arith_imm(ctx, op, rt, rs, imm);
|
||||
}
|
||||
break;
|
||||
case OPC_ADDIU:
|
||||
gen_arith_imm(ctx, op, rt, rs, imm);
|
||||
break;
|
||||
|
@ -16081,9 +16418,58 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
|
|||
offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
|
||||
gen_compute_branch(ctx, op, 4, rs, rt, offset);
|
||||
break;
|
||||
case OPC_BEQL ... OPC_BGTZL: /* Branch */
|
||||
/* Branch */
|
||||
case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */
|
||||
if (ctx->insn_flags & ISA_MIPS32R6) {
|
||||
if (rt == 0) {
|
||||
generate_exception(ctx, EXCP_RI);
|
||||
break;
|
||||
}
|
||||
/* OPC_BLEZC, OPC_BGEZC, OPC_BGEC */
|
||||
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
|
||||
} else {
|
||||
/* OPC_BLEZL */
|
||||
gen_compute_branch(ctx, op, 4, rs, rt, imm << 2);
|
||||
}
|
||||
break;
|
||||
case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */
|
||||
if (ctx->insn_flags & ISA_MIPS32R6) {
|
||||
if (rt == 0) {
|
||||
generate_exception(ctx, EXCP_RI);
|
||||
break;
|
||||
}
|
||||
/* OPC_BGTZC, OPC_BLTZC, OPC_BLTC */
|
||||
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
|
||||
} else {
|
||||
/* OPC_BGTZL */
|
||||
gen_compute_branch(ctx, op, 4, rs, rt, imm << 2);
|
||||
}
|
||||
break;
|
||||
case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC, OPC_BLEZ */
|
||||
if (rt == 0) {
|
||||
/* OPC_BLEZ */
|
||||
gen_compute_branch(ctx, op, 4, rs, rt, imm << 2);
|
||||
} else {
|
||||
check_insn(ctx, ISA_MIPS32R6);
|
||||
/* OPC_BLEZALC, OPC_BGEZALC, OPC_BGEUC */
|
||||
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
|
||||
}
|
||||
break;
|
||||
case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC, OPC_BGTZ */
|
||||
if (rt == 0) {
|
||||
/* OPC_BGTZ */
|
||||
gen_compute_branch(ctx, op, 4, rs, rt, imm << 2);
|
||||
} else {
|
||||
check_insn(ctx, ISA_MIPS32R6);
|
||||
/* OPC_BGTZALC, OPC_BLTZALC, OPC_BLTUC */
|
||||
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
|
||||
}
|
||||
break;
|
||||
case OPC_BEQL:
|
||||
case OPC_BNEL:
|
||||
check_insn_opc_removed(ctx, ISA_MIPS32R6);
|
||||
case OPC_BEQ ... OPC_BGTZ:
|
||||
case OPC_BEQ:
|
||||
case OPC_BNE:
|
||||
gen_compute_branch(ctx, op, 4, rs, rt, imm << 2);
|
||||
break;
|
||||
case OPC_LWL: /* Load and stores */
|
||||
|
@ -16146,7 +16532,24 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
|
|||
gen_cp1(ctx, op1, rt, rd);
|
||||
break;
|
||||
#endif
|
||||
case OPC_BC1ANY2:
|
||||
case OPC_BC1EQZ: /* OPC_BC1ANY2 */
|
||||
if (ctx->insn_flags & ISA_MIPS32R6) {
|
||||
/* OPC_BC1EQZ */
|
||||
gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode),
|
||||
rt, imm << 2);
|
||||
} else {
|
||||
/* OPC_BC1ANY2 */
|
||||
check_cop1x(ctx);
|
||||
check_insn(ctx, ASE_MIPS3D);
|
||||
gen_compute_branch1(ctx, MASK_BC1(ctx->opcode),
|
||||
(rt >> 2) & 0x7, imm << 2);
|
||||
}
|
||||
break;
|
||||
case OPC_BC1NEZ:
|
||||
check_insn(ctx, ISA_MIPS32R6);
|
||||
gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode),
|
||||
rt, imm << 2);
|
||||
break;
|
||||
case OPC_BC1ANY4:
|
||||
check_insn_opc_removed(ctx, ISA_MIPS32R6);
|
||||
check_cop1x(ctx);
|
||||
|
@ -16176,13 +16579,35 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
|
|||
}
|
||||
break;
|
||||
|
||||
/* COP2. */
|
||||
case OPC_LWC2:
|
||||
case OPC_LDC2:
|
||||
case OPC_SWC2:
|
||||
case OPC_SDC2:
|
||||
/* Compact branches [R6] and COP2 [non-R6] */
|
||||
case OPC_BC: /* OPC_LWC2 */
|
||||
case OPC_BALC: /* OPC_SWC2 */
|
||||
if (ctx->insn_flags & ISA_MIPS32R6) {
|
||||
/* OPC_BC, OPC_BALC */
|
||||
gen_compute_compact_branch(ctx, op, 0, 0,
|
||||
sextract32(ctx->opcode << 2, 0, 28));
|
||||
} else {
|
||||
/* OPC_LWC2, OPC_SWC2 */
|
||||
/* COP2: Not implemented. */
|
||||
generate_exception_err(ctx, EXCP_CpU, 2);
|
||||
}
|
||||
break;
|
||||
case OPC_BEQZC: /* OPC_JIC, OPC_LDC2 */
|
||||
case OPC_BNEZC: /* OPC_JIALC, OPC_SDC2 */
|
||||
if (ctx->insn_flags & ISA_MIPS32R6) {
|
||||
if (rs != 0) {
|
||||
/* OPC_BEQZC, OPC_BNEZC */
|
||||
gen_compute_compact_branch(ctx, op, rs, 0,
|
||||
sextract32(ctx->opcode << 2, 0, 23));
|
||||
} else {
|
||||
/* OPC_JIC, OPC_JIALC */
|
||||
gen_compute_compact_branch(ctx, op, 0, rt, imm);
|
||||
}
|
||||
} else {
|
||||
/* OPC_LWC2, OPC_SWC2 */
|
||||
/* COP2: Not implemented. */
|
||||
generate_exception_err(ctx, EXCP_CpU, 2);
|
||||
}
|
||||
break;
|
||||
case OPC_CP2:
|
||||
check_insn(ctx, INSN_LOONGSON2F);
|
||||
|
@ -16256,12 +16681,31 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
|
|||
check_mips_64(ctx);
|
||||
gen_st_cond(ctx, op, rt, rs, imm);
|
||||
break;
|
||||
case OPC_DADDI:
|
||||
case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */
|
||||
if (ctx->insn_flags & ISA_MIPS32R6) {
|
||||
/* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */
|
||||
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
|
||||
} else {
|
||||
/* OPC_DADDI */
|
||||
check_insn(ctx, ISA_MIPS3);
|
||||
check_mips_64(ctx);
|
||||
gen_arith_imm(ctx, op, rt, rs, imm);
|
||||
}
|
||||
break;
|
||||
case OPC_DADDIU:
|
||||
check_insn(ctx, ISA_MIPS3);
|
||||
check_mips_64(ctx);
|
||||
gen_arith_imm(ctx, op, rt, rs, imm);
|
||||
break;
|
||||
#else
|
||||
case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */
|
||||
if (ctx->insn_flags & ISA_MIPS32R6) {
|
||||
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
|
||||
} else {
|
||||
MIPS_INVAL("major opcode");
|
||||
generate_exception(ctx, EXCP_RI);
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
case OPC_JALX:
|
||||
check_insn(ctx, ASE_MIPS16 | ASE_MICROMIPS);
|
||||
|
@ -16368,8 +16812,9 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
|
|||
ctx.bstate = BS_STOP;
|
||||
break;
|
||||
}
|
||||
|
||||
if (is_delay) {
|
||||
handle_delay_slot(&ctx, insn_bytes);
|
||||
gen_branch(&ctx, insn_bytes);
|
||||
}
|
||||
ctx.pc += insn_bytes;
|
||||
|
||||
|
|
Loading…
Reference in a new issue