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target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructions

Browse source 
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Yongbok Kim 2014-06-27 08:49:05 +01:00 committed by Leon Alrae
parent 01f7288579
commit 15eacb9b52
4 changed files with 140 additions and 12 deletions
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4
disas/mips.c
View file

@ -1246,6 +1246,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"cache", "k,o(b)", 0x7c000025, 0xfc00007f, RD_b, 0, I32R6},
{"seleqz", "d,v,t", 0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
{"selnez", "d,v,t", 0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
{"align", "d,v,t", 0x7c000220, 0xfc00073f, WR_d|RD_s|RD_t, 0, I32R6},
{"dalign", "d,v,t", 0x7c000224, 0xfc00063f, WR_d|RD_s|RD_t, 0, I64R6},
{"bitswap", "d,w", 0x7c000020, 0xffe007ff, WR_d|RD_t, 0, I32R6},
{"dbitswap","d,w", 0x7c000024, 0xffe007ff, WR_d|RD_t, 0, I64R6},
{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4|I32|G3 },
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4|I33 },
{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */

5
target-mips/helper.h
View file

@ -39,6 +39,11 @@ DEF_HELPER_3(macchiu, tl, env, tl, tl)
DEF_HELPER_3(msachi, tl, env, tl, tl)
DEF_HELPER_3(msachiu, tl, env, tl, tl)
DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl)
#ifdef TARGET_MIPS64
DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl)
#endif
#ifndef CONFIG_USER_ONLY
/* CP0 helpers */
DEF_HELPER_1(mfc0_mvpcontrol, tl, env)

23
target-mips/op_helper.c
View file

@ -266,6 +266,29 @@ target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
(uint64_t)(uint32_t)arg2);
}
static inline target_ulong bitswap(target_ulong v)
{
v = ((v >> 1) & (target_ulong)0x5555555555555555) |
((v & (target_ulong)0x5555555555555555) << 1);
v = ((v >> 2) & (target_ulong)0x3333333333333333) |
((v & (target_ulong)0x3333333333333333) << 2);
v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0F) |
((v & (target_ulong)0x0F0F0F0F0F0F0F0F) << 4);
return v;
}
#ifdef TARGET_MIPS64
target_ulong helper_dbitswap(target_ulong rt)
{
return bitswap(rt);
}
#endif
target_ulong helper_bitswap(target_ulong rt)
{
return (int32_t)bitswap(rt);
}
#ifndef CONFIG_USER_ONLY
static inline hwaddr do_translate_address(CPUMIPSState *env,

120
target-mips/translate.c
View file

@ -392,17 +392,23 @@ enum {
#define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
enum {
OPC_WSBH = (0x02 << 6) | OPC_BSHFL,
OPC_SEB = (0x10 << 6) | OPC_BSHFL,
OPC_SEH = (0x18 << 6) | OPC_BSHFL,
OPC_WSBH = (0x02 << 6) | OPC_BSHFL,
OPC_SEB = (0x10 << 6) | OPC_BSHFL,
OPC_SEH = (0x18 << 6) | OPC_BSHFL,
OPC_ALIGN = (0x08 << 6) | OPC_BSHFL, /* 010.bp */
OPC_ALIGN_END = (0x0B << 6) | OPC_BSHFL, /* 010.00 to 010.11 */
OPC_BITSWAP = (0x00 << 6) | OPC_BSHFL /* 00000 */
};
/* DBSHFL opcodes */
#define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
enum {
OPC_DSBH = (0x02 << 6) | OPC_DBSHFL,
OPC_DSHD = (0x05 << 6) | OPC_DBSHFL,
OPC_DSBH = (0x02 << 6) | OPC_DBSHFL,
OPC_DSHD = (0x05 << 6) | OPC_DBSHFL,
OPC_DALIGN = (0x08 << 6) | OPC_DBSHFL, /* 01.bp */
OPC_DALIGN_END = (0x0F << 6) | OPC_DBSHFL, /* 01.000 to 01.111 */
OPC_DBITSWAP = (0x00 << 6) | OPC_DBSHFL, /* 00000 */
};
/* MIPS DSP REGIMM opcodes */
@ -15162,12 +15168,14 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
{
int rs, rt;
uint32_t op1;
int rs, rt, rd, sa;
uint32_t op1, op2;
int16_t imm;
rs = (ctx->opcode >> 21) & 0x1f;
rt = (ctx->opcode >> 16) & 0x1f;
rd = (ctx->opcode >> 11) & 0x1f;
sa = (ctx->opcode >> 6) & 0x1f;
imm = (int16_t)ctx->opcode >> 7;
op1 = MASK_SPECIAL3(ctx->opcode);
@ -15188,6 +15196,43 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
case R6_OPC_LL:
gen_ld(ctx, op1, rt, rs, imm);
break;
case OPC_BSHFL:
{
if (rd == 0) {
/* Treat as NOP. */
break;
}
TCGv t0 = tcg_temp_new();
gen_load_gpr(t0, rt);
op2 = MASK_BSHFL(ctx->opcode);
switch (op2) {
case OPC_ALIGN ... OPC_ALIGN_END:
sa &= 3;
if (sa == 0) {
tcg_gen_mov_tl(cpu_gpr[rd], t0);
} else {
TCGv t1 = tcg_temp_new();
TCGv_i64 t2 = tcg_temp_new_i64();
gen_load_gpr(t1, rs);
tcg_gen_concat_tl_i64(t2, t1, t0);
tcg_gen_shri_i64(t2, t2, 8 * (4 - sa));
#if defined(TARGET_MIPS64)
tcg_gen_ext32s_i64(cpu_gpr[rd], t2);
#else
tcg_gen_trunc_i64_i32(cpu_gpr[rd], t2);
#endif
tcg_temp_free_i64(t2);
tcg_temp_free(t1);
}
break;
case OPC_BITSWAP:
gen_helper_bitswap(cpu_gpr[rd], t0);
break;
}
tcg_temp_free(t0);
}
break;
#if defined(TARGET_MIPS64)
case R6_OPC_SCD:
gen_st_cond(ctx, op1, rt, rs, imm);
@ -15195,6 +15240,38 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
case R6_OPC_LLD:
gen_ld(ctx, op1, rt, rs, imm);
break;
case OPC_DBSHFL:
check_mips_64(ctx);
{
if (rd == 0) {
/* Treat as NOP. */
break;
}
TCGv t0 = tcg_temp_new();
gen_load_gpr(t0, rt);
op2 = MASK_DBSHFL(ctx->opcode);
switch (op2) {
case OPC_DALIGN ... OPC_DALIGN_END:
sa &= 7;
if (sa == 0) {
tcg_gen_mov_tl(cpu_gpr[rd], t0);
} else {
TCGv t1 = tcg_temp_new();
gen_load_gpr(t1, rs);
tcg_gen_shli_tl(t0, t0, 8 * sa);
tcg_gen_shri_tl(t1, t1, 8 * (8 - sa));
tcg_gen_or_tl(cpu_gpr[rd], t1, t0);
tcg_temp_free(t1);
}
break;
case OPC_DBITSWAP:
gen_helper_dbitswap(cpu_gpr[rd], t0);
break;
}
tcg_temp_free(t0);
}
break;
#endif
default: /* Invalid */
MIPS_INVAL("special3_r6");
@ -15743,9 +15820,18 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
gen_bitops(ctx, op1, rt, rs, sa, rd);
break;
case OPC_BSHFL:
check_insn(ctx, ISA_MIPS32R2);
op2 = MASK_BSHFL(ctx->opcode);
gen_bshfl(ctx, op2, rt, rd);
switch (op2) {
case OPC_ALIGN ... OPC_ALIGN_END:
case OPC_BITSWAP:
check_insn(ctx, ISA_MIPS32R6);
decode_opc_special3_r6(env, ctx);
break;
default:
check_insn(ctx, ISA_MIPS32R2);
gen_bshfl(ctx, op2, rt, rd);
break;
}
break;
#if defined(TARGET_MIPS64)
case OPC_DEXTM ... OPC_DEXT:
@ -15755,10 +15841,20 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
gen_bitops(ctx, op1, rt, rs, sa, rd);
break;
case OPC_DBSHFL:
check_insn(ctx, ISA_MIPS64R2);
check_mips_64(ctx);
op2 = MASK_DBSHFL(ctx->opcode);
gen_bshfl(ctx, op2, rt, rd);
switch (op2) {
case OPC_DALIGN ... OPC_DALIGN_END:
case OPC_DBITSWAP:
check_insn(ctx, ISA_MIPS32R6);
decode_opc_special3_r6(env, ctx);
break;
default:
check_insn(ctx, ISA_MIPS64R2);
check_mips_64(ctx);
op2 = MASK_DBSHFL(ctx->opcode);
gen_bshfl(ctx, op2, rt, rd);
break;
}
break;
#endif
case OPC_RDHWR: