Jisheng Zhang c3dffa879c riscv: dts: sophgo: add initial CV1800B SoC device tree ... Add initial device tree for the CV1800B RISC-V SoC by SOPHGO. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>		2023-10-07 14:17:12 +01:00
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allwinner	riscv: dts: allwinner: d1: Add CAN controller nodes	2023-08-13 14:12:35 +08:00
canaan	riscv: dts: canaan: drop invalid spi-max-frequency	2023-03-26 23:58:27 +01:00
microchip	riscv: dts: microchip: fix the mpfs' mailbox regs	2023-03-15 14:43:48 +00:00
renesas	riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy node	2023-07-25 11:41:09 +02:00
sifive	SoC: DT changes for 6.3	2023-02-20 15:49:56 -08:00
sophgo	riscv: dts: sophgo: add initial CV1800B SoC device tree	2023-10-07 14:17:12 +01:00
starfive	riscv: dts: starfive: add assigned-clock* to limit frquency	2023-09-30 09:58:30 +01:00
thead	riscv: dts: change TH1520 files to dual license	2023-08-16 18:59:30 +01:00
Makefile	riscv: dts: sophgo: add Milk-V Pioneer board device tree	2023-10-07 11:17:01 +01:00