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The ARC SDP I2S clock can be programmed using a specific PLL. This patch has the goal of adding a clock driver that programs this PLL. At this moment the rate values are hardcoded in a table but in the future it would be ideal to use a function which determines the PLL values given the desired rate. Signed-off-by: Jose Abreu <joabreu@synopsys.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
26 lines
672 B
Plaintext
26 lines
672 B
Plaintext
Binding for the AXS10X I2S PLL clock
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible: shall be "snps,axs10x-i2s-pll-clock"
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- reg : address and length of the I2S PLL register set.
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- clocks: shall be the input parent clock phandle for the PLL.
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- #clock-cells: from common clock binding; Should always be set to 0.
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Example:
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pll_clock: pll_clock {
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compatible = "fixed-clock";
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clock-frequency = <27000000>;
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#clock-cells = <0>;
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};
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i2s_clock@100a0 {
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compatible = "snps,axs10x-i2s-pll-clock";
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reg = <0x100a0 0x10>;
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clocks = <&pll_clock>;
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#clock-cells = <0>;
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};
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