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arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata
Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore suffers from all the same errata. CC: stable@vger.kernel.org # 5.15+ Signed-off-by: Easwar Hariharan <eahariha@linux.microsoft.com> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20240214175522.2457857-1-eahariha@linux.microsoft.com Signed-off-by: Will Deacon <will@kernel.org>
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@ -243,3 +243,10 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| ASR | ASR8601 | #8601001 | N/A |
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| ASR | ASR8601 | #8601001 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| Microsoft | Azure Cobalt 100| #2139208 | ARM64_ERRATUM_2139208 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Microsoft | Azure Cobalt 100| #2067961 | ARM64_ERRATUM_2067961 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Microsoft | Azure Cobalt 100| #2253138 | ARM64_ERRATUM_2253138 |
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+----------------+-----------------+-----------------+-----------------------------+
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@ -61,6 +61,7 @@
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#define ARM_CPU_IMP_HISI 0x48
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#define ARM_CPU_IMP_HISI 0x48
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#define ARM_CPU_IMP_APPLE 0x61
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#define ARM_CPU_IMP_APPLE 0x61
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#define ARM_CPU_IMP_AMPERE 0xC0
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#define ARM_CPU_IMP_AMPERE 0xC0
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#define ARM_CPU_IMP_MICROSOFT 0x6D
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#define ARM_CPU_PART_AEM_V8 0xD0F
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#define ARM_CPU_PART_AEM_V8 0xD0F
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#define ARM_CPU_PART_FOUNDATION 0xD00
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#define ARM_CPU_PART_FOUNDATION 0xD00
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@ -135,6 +136,8 @@
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#define AMPERE_CPU_PART_AMPERE1 0xAC3
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#define AMPERE_CPU_PART_AMPERE1 0xAC3
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#define MICROSOFT_CPU_PART_AZURE_COBALT_100 0xD49 /* Based on r0p0 of ARM Neoverse N2 */
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#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
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#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
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#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
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#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
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#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
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#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
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@ -193,6 +196,7 @@
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#define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)
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#define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)
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#define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)
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#define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)
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#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
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#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
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#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100)
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/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
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/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
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#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
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#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
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@ -374,6 +374,7 @@ static const struct midr_range erratum_1463225[] = {
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static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
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static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
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#ifdef CONFIG_ARM64_ERRATUM_2139208
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#ifdef CONFIG_ARM64_ERRATUM_2139208
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
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MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
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#endif
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_2119858
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#ifdef CONFIG_ARM64_ERRATUM_2119858
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
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@ -387,6 +388,7 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
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static const struct midr_range tsb_flush_fail_cpus[] = {
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static const struct midr_range tsb_flush_fail_cpus[] = {
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#ifdef CONFIG_ARM64_ERRATUM_2067961
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#ifdef CONFIG_ARM64_ERRATUM_2067961
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
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MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
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#endif
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_2054223
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#ifdef CONFIG_ARM64_ERRATUM_2054223
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
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@ -399,6 +401,7 @@ static const struct midr_range tsb_flush_fail_cpus[] = {
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static struct midr_range trbe_write_out_of_range_cpus[] = {
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static struct midr_range trbe_write_out_of_range_cpus[] = {
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#ifdef CONFIG_ARM64_ERRATUM_2253138
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#ifdef CONFIG_ARM64_ERRATUM_2253138
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
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MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
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#endif
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_2224489
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#ifdef CONFIG_ARM64_ERRATUM_2224489
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
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