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RISC-V Patches for the 6.3 Merge Window, Part 2
* Some cleanups and fixes for the Zbb-optimized string routines. * Support for custom (vendor or implementation defined) perf events. * COMMAND_LINE_SIZE has been increased to 1024. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmQBuDMTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYie2nEACDnj2w35BYDZDrbOiodXw1bA60IpJG 5Q3bZEIWimaoDluD52UxrLhAZgJ3imGHF2nLLevqqsqAWKT2aRxsiEtgqARN0GzW Am2+ZBdMuo1oCOHhIzCI9nk1xMG1fjva1ZAhGcVK876W3NuLUDvb1+LeDcwZB5bX 8KUu1haILIlngd8xOZE88xJOw83uQaF1Oc1NLqpQabbCiWxFBAIzI3O/7ZyuVk4M LrdD5zH7YBUpksol0CxWaJ/jI59t23na2421NKNm34zALsvVFSKc2CZ0+r5DFy3D 4bzMdzXmtDjWfSCTGicGk03acrxUwgpAkFH/y2eJzhQl1WWrO/FiUzlI2uKoHou9 MO+fxPHcOamnWH5OF8jzP9+v5fkKIX2eYWJl5E3Jge6KU8D1Y2cPbE/k75cOq70Y BVF+BUnQ26UdqYH0POFqikizF7dvt6G+rNpUnFrufc6xs+BALxfyIHRQnTw8dQu4 FbZRLX9YNn8/TpwcfnzIzFk1CH35n8QPBvcumIiV/344Gs7nt5vyDO7b//ExS4IL mrENDNdaQ/u8T6xkhGSWPPMwNAj3OFpLRi00BInYvRXx9/0WArD1Z5N9uMl42dqd kB060nUH1Ao7aBQJztqZVDOYwyFhREGM+xLRBLE+CiD8EnVvm30Fhovq2FrFfbif GPHt+ouKJtlkTw== =68ZK -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.3-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull more RISC-V updates from Palmer Dabbelt: - Some cleanups and fixes for the Zbb-optimized string routines - Support for custom (vendor or implementation defined) perf events - COMMAND_LINE_SIZE has been increased to 1024 * tag 'riscv-for-linus-6.3-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: Bump COMMAND_LINE_SIZE value to 1024 drivers/perf: RISC-V: Allow programming custom firmware events riscv, lib: Fix Zbb strncmp RISC-V: improve string-function assembly
This commit is contained in:
commit
bf1a1bad82
8
arch/riscv/include/uapi/asm/setup.h
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arch/riscv/include/uapi/asm/setup.h
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@ -0,0 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
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#ifndef _UAPI_ASM_RISCV_SETUP_H
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#define _UAPI_ASM_RISCV_SETUP_H
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#define COMMAND_LINE_SIZE 1024
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#endif /* _UAPI_ASM_RISCV_SETUP_H */
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@ -40,7 +40,9 @@ SYM_FUNC_START(strcmp)
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ret
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ret
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/*
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/*
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* Variant of strcmp using the ZBB extension if available
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* Variant of strcmp using the ZBB extension if available.
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* The code was published as part of the bitmanip manual
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* in Appendix A.
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*/
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*/
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#ifdef CONFIG_RISCV_ISA_ZBB
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#ifdef CONFIG_RISCV_ISA_ZBB
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strcmp_zbb:
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strcmp_zbb:
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@ -57,7 +59,7 @@ strcmp_zbb:
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* a1 - string2
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* a1 - string2
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*
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*
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* Clobbers
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* Clobbers
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* t0, t1, t2, t3, t4, t5
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* t0, t1, t2, t3, t4
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*/
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*/
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or t2, a0, a1
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or t2, a0, a1
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@ -96,7 +96,7 @@ strlen_zbb:
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* of valid bytes in this chunk.
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* of valid bytes in this chunk.
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*/
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*/
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srli a0, t1, 3
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srli a0, t1, 3
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bgtu t3, a0, 3f
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bgtu t3, a0, 2f
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/* Prepare for the word comparison loop. */
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/* Prepare for the word comparison loop. */
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addi t2, t0, SZREG
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addi t2, t0, SZREG
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@ -112,20 +112,20 @@ strlen_zbb:
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addi t0, t0, SZREG
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addi t0, t0, SZREG
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orc.b t1, t1
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orc.b t1, t1
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beq t1, t3, 1b
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beq t1, t3, 1b
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2:
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not t1, t1
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not t1, t1
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CZ t1, t1
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CZ t1, t1
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srli t1, t1, 3
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/* Get number of processed words. */
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/* Get number of processed bytes. */
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sub t2, t0, t2
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sub t2, t0, t2
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/* Add number of characters in the first word. */
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/* Add number of characters in the first word. */
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add a0, a0, t2
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add a0, a0, t2
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srli t1, t1, 3
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/* Add number of characters in the last word. */
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/* Add number of characters in the last word. */
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add a0, a0, t1
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add a0, a0, t1
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3:
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2:
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ret
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ret
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.option pop
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.option pop
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@ -70,7 +70,7 @@ strncmp_zbb:
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li t5, -1
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li t5, -1
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and t2, t2, SZREG-1
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and t2, t2, SZREG-1
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add t4, a0, a2
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add t4, a0, a2
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bnez t2, 4f
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bnez t2, 3f
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/* Adjust limit for fast-path. */
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/* Adjust limit for fast-path. */
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andi t6, t4, -SZREG
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andi t6, t4, -SZREG
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@ -78,11 +78,13 @@ strncmp_zbb:
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/* Main loop for aligned string. */
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/* Main loop for aligned string. */
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.p2align 3
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.p2align 3
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1:
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1:
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bgt a0, t6, 3f
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bge a0, t6, 3f
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REG_L t0, 0(a0)
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REG_L t0, 0(a0)
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REG_L t1, 0(a1)
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REG_L t1, 0(a1)
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orc.b t3, t0
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orc.b t3, t0
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bne t3, t5, 2f
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bne t3, t5, 2f
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orc.b t3, t1
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bne t3, t5, 2f
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addi a0, a0, SZREG
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addi a0, a0, SZREG
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addi a1, a1, SZREG
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addi a1, a1, SZREG
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beq t0, t1, 1b
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beq t0, t1, 1b
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@ -114,23 +116,21 @@ strncmp_zbb:
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ret
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ret
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/* Simple loop for misaligned strings. */
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/* Simple loop for misaligned strings. */
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3:
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/* Restore limit for slow-path. */
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.p2align 3
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.p2align 3
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4:
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3:
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bge a0, t4, 6f
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bge a0, t4, 5f
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lbu t0, 0(a0)
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lbu t0, 0(a0)
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lbu t1, 0(a1)
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lbu t1, 0(a1)
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addi a0, a0, 1
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addi a0, a0, 1
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addi a1, a1, 1
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addi a1, a1, 1
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bne t0, t1, 5f
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bne t0, t1, 4f
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bnez t0, 4b
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bnez t0, 3b
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5:
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4:
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sub a0, t0, t1
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sub a0, t0, t1
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ret
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ret
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6:
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5:
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li a0, 0
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li a0, 0
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ret
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ret
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@ -436,11 +436,8 @@ static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig)
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bSoftware = config >> 63;
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bSoftware = config >> 63;
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raw_config_val = config & RISCV_PMU_RAW_EVENT_MASK;
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raw_config_val = config & RISCV_PMU_RAW_EVENT_MASK;
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if (bSoftware) {
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if (bSoftware) {
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if (raw_config_val < SBI_PMU_FW_MAX)
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ret = (raw_config_val & 0xFFFF) |
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ret = (raw_config_val & 0xFFFF) |
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(SBI_PMU_EVENT_TYPE_FW << 16);
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(SBI_PMU_EVENT_TYPE_FW << 16);
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else
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return -EINVAL;
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} else {
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} else {
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ret = RISCV_PMU_RAW_EVENT_IDX;
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ret = RISCV_PMU_RAW_EVENT_IDX;
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*econfig = raw_config_val;
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*econfig = raw_config_val;
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