From 6934cf8a3e0b4a8318ce8f1342348e967e29192f Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 8 Feb 2023 23:53:28 +0100 Subject: [PATCH 1/4] RISC-V: improve string-function assembly Adapt the suggestions for the assembly string functions that Andrew suggested but that I didn't manage to include into the series that got applied. This includes improvements to two comments, removal of unneeded labels and moving one instruction slightly higher to contradict an explanatory comment. Suggested-by: Andrew Jones Signed-off-by: Heiko Stuebner Reviewed-by: Andrew Jones Tested-by: Conor Dooley Link: https://lore.kernel.org/r/20230208225328.1636017-3-heiko@sntech.de Signed-off-by: Palmer Dabbelt --- arch/riscv/lib/strcmp.S | 6 ++++-- arch/riscv/lib/strlen.S | 10 +++++----- arch/riscv/lib/strncmp.S | 16 +++++++--------- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/riscv/lib/strcmp.S b/arch/riscv/lib/strcmp.S index 986ab23fe787..c42a8412547f 100644 --- a/arch/riscv/lib/strcmp.S +++ b/arch/riscv/lib/strcmp.S @@ -40,7 +40,9 @@ SYM_FUNC_START(strcmp) ret /* - * Variant of strcmp using the ZBB extension if available + * Variant of strcmp using the ZBB extension if available. + * The code was published as part of the bitmanip manual + * in Appendix A. */ #ifdef CONFIG_RISCV_ISA_ZBB strcmp_zbb: @@ -57,7 +59,7 @@ strcmp_zbb: * a1 - string2 * * Clobbers - * t0, t1, t2, t3, t4, t5 + * t0, t1, t2, t3, t4 */ or t2, a0, a1 diff --git a/arch/riscv/lib/strlen.S b/arch/riscv/lib/strlen.S index 8345ceeee3f6..15bb8f3aa959 100644 --- a/arch/riscv/lib/strlen.S +++ b/arch/riscv/lib/strlen.S @@ -96,7 +96,7 @@ strlen_zbb: * of valid bytes in this chunk. */ srli a0, t1, 3 - bgtu t3, a0, 3f + bgtu t3, a0, 2f /* Prepare for the word comparison loop. */ addi t2, t0, SZREG @@ -112,20 +112,20 @@ strlen_zbb: addi t0, t0, SZREG orc.b t1, t1 beq t1, t3, 1b -2: + not t1, t1 CZ t1, t1 + srli t1, t1, 3 - /* Get number of processed words. */ + /* Get number of processed bytes. */ sub t2, t0, t2 /* Add number of characters in the first word. */ add a0, a0, t2 - srli t1, t1, 3 /* Add number of characters in the last word. */ add a0, a0, t1 -3: +2: ret .option pop diff --git a/arch/riscv/lib/strncmp.S b/arch/riscv/lib/strncmp.S index ee49595075be..e09de79e62b9 100644 --- a/arch/riscv/lib/strncmp.S +++ b/arch/riscv/lib/strncmp.S @@ -70,7 +70,7 @@ strncmp_zbb: li t5, -1 and t2, t2, SZREG-1 add t4, a0, a2 - bnez t2, 4f + bnez t2, 3f /* Adjust limit for fast-path. */ andi t6, t4, -SZREG @@ -114,23 +114,21 @@ strncmp_zbb: ret /* Simple loop for misaligned strings. */ -3: - /* Restore limit for slow-path. */ .p2align 3 -4: - bge a0, t4, 6f +3: + bge a0, t4, 5f lbu t0, 0(a0) lbu t1, 0(a1) addi a0, a0, 1 addi a1, a1, 1 - bne t0, t1, 5f - bnez t0, 4b + bne t0, t1, 4f + bnez t0, 3b -5: +4: sub a0, t0, t1 ret -6: +5: li a0, 0 ret From 81a1dd10b072fd432f37cd5dc9eb3ed6ec5d386e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= Date: Tue, 28 Feb 2023 19:42:10 +0100 Subject: [PATCH 2/4] riscv, lib: Fix Zbb strncmp MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Zbb optimized strncmp has two parts; a fast path that does XLEN/8B per iteration, and a slow that does one byte per iteration. The idea is to compare aligned XLEN chunks for most of strings, and do the remainder tail in the slow path. The Zbb strncmp has two issues in the fast path: Incorrect remainder handling (wrong compare): Assume that the string length is 9. On 64b systems, the fast path should do one iteration, and one iteration in the slow path. Instead, both were done in the fast path, which lead to incorrect results. An example: strncmp("/dev/vda", "/dev/", 5); Correct by changing "bgt" to "bge". Missing NULL checks in the second string: This could lead to incorrect results for: strncmp("/dev/vda", "/dev/vda\0", 8); Correct by adding an additional check. Fixes: b6fcdb191e36 ("RISC-V: add zbb support to string functions") Suggested-by: Heiko Stuebner Signed-off-by: Björn Töpel Tested-by: Conor Dooley Tested-by: Guenter Roeck Link: https://lore.kernel.org/r/20230228184211.1585641-1-bjorn@kernel.org Signed-off-by: Palmer Dabbelt --- arch/riscv/lib/strncmp.S | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/lib/strncmp.S b/arch/riscv/lib/strncmp.S index e09de79e62b9..7ac2f667285a 100644 --- a/arch/riscv/lib/strncmp.S +++ b/arch/riscv/lib/strncmp.S @@ -78,11 +78,13 @@ strncmp_zbb: /* Main loop for aligned string. */ .p2align 3 1: - bgt a0, t6, 3f + bge a0, t6, 3f REG_L t0, 0(a0) REG_L t1, 0(a1) orc.b t3, t0 bne t3, t5, 2f + orc.b t3, t1 + bne t3, t5, 2f addi a0, a0, SZREG addi a1, a1, SZREG beq t0, t1, 1b From 9f828bc3fb900c5d39ec13ea150341d28fb1f158 Mon Sep 17 00:00:00 2001 From: Mayuresh Chitale Date: Wed, 8 Feb 2023 13:13:14 +0530 Subject: [PATCH 3/4] drivers/perf: RISC-V: Allow programming custom firmware events Applications need to be able to program the SBI implementation specific or custom firmware events in addition to the standard firmware events. Remove a check in the driver that prohibits the programming of the custom firmware events. Signed-off-by: Mayuresh Chitale Reviewed-by: Andrew Jones Link: https://lore.kernel.org/r/20230208074314.3661406-1-mchitale@ventanamicro.com Signed-off-by: Palmer Dabbelt --- drivers/perf/riscv_pmu_sbi.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 7b2288d4b1ec..8bd27d795253 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -385,11 +385,8 @@ static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig) bSoftware = config >> 63; raw_config_val = config & RISCV_PMU_RAW_EVENT_MASK; if (bSoftware) { - if (raw_config_val < SBI_PMU_FW_MAX) - ret = (raw_config_val & 0xFFFF) | - (SBI_PMU_EVENT_TYPE_FW << 16); - else - return -EINVAL; + ret = (raw_config_val & 0xFFFF) | + (SBI_PMU_EVENT_TYPE_FW << 16); } else { ret = RISCV_PMU_RAW_EVENT_IDX; *econfig = raw_config_val; From 61fc1ee8be26bc192d691932b0a67eabee45d12f Mon Sep 17 00:00:00 2001 From: Alexandre Ghiti Date: Tue, 16 Mar 2021 15:34:20 -0400 Subject: [PATCH 4/4] riscv: Bump COMMAND_LINE_SIZE value to 1024 Increase COMMAND_LINE_SIZE as the current default value is too low for syzbot kernel command line. There has been considerable discussion on this patch that has led to a larger patch set removing COMMAND_LINE_SIZE from the uapi headers on all ports. That's not quite done yet, but it's gotten far enough we're confident this is not a uABI change so this is safe. Reported-by: Dmitry Vyukov Signed-off-by: Alexandre Ghiti Link: https://lore.kernel.org/r/20210316193420.904-1-alex@ghiti.fr [Palmer: it's not uabi] Link: https://lore.kernel.org/linux-riscv/874b8076-b0d1-4aaa-bcd8-05d523060152@app.fastmail.com/#t Signed-off-by: Palmer Dabbelt --- arch/riscv/include/uapi/asm/setup.h | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 arch/riscv/include/uapi/asm/setup.h diff --git a/arch/riscv/include/uapi/asm/setup.h b/arch/riscv/include/uapi/asm/setup.h new file mode 100644 index 000000000000..66b13a522880 --- /dev/null +++ b/arch/riscv/include/uapi/asm/setup.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ + +#ifndef _UAPI_ASM_RISCV_SETUP_H +#define _UAPI_ASM_RISCV_SETUP_H + +#define COMMAND_LINE_SIZE 1024 + +#endif /* _UAPI_ASM_RISCV_SETUP_H */