mirror of
https://github.com/torvalds/linux
synced 2024-10-03 09:48:02 +00:00
drm fixes for 5.11-rc7
ttm: - fix huge page warning regression i915: - Skip vswing programming for TBT - Power up combo PHY lanes for HDMI - Fix double YUV range correction on HDR planes - Fix the MST PBN divider calculation - Fix LTTPR vswing/pre-emp setting in non-transparent mode - Move the breadcrumb to the signaler if completed upon cancel - Close race between enable_breadcrumbs and cancel_breadcrumbs - Drop lru bumping on display unpinning amdgpu: - Fix retry in gem create - Vangogh fixes - Fix for display from shared buffers - Various display fixes amdkfd: - Fix regression in buffer free nouveau: - fix DMA API warning regression drm/bridge/lontium-lt9611uxc: - EDID fixes - Don't handle hotplug events in IRQ handler -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJgHKD+AAoJEAx081l5xIa+XXsQAKlhnEE72yA4qHCPnC8WM6jg CQGJGFpFY0woaWoRVuH/kSz+gH0ksLENQWmT0vrG1nA35fp5ypsB2sQLq7lQGOgm kcKtW8ykwz/m7JETeN5R5+GXHgZIQDcMjqVdXA8drFCX0RzgTD/rdtFN+XZTAS9z c8Sxr0+nUMIIqJCYeWe6MNvTUDxE9N34Kcm8dfELkYXBmqakbo9Mrx1ENEuM4f1r mIJgKTGttSsRIduoqOcTY5BEMzAzpuETWhQzaIDSUMHyz5PuzpLABbQ3Fn9ubjyu wEnEqNrUtrcOq2cy19L3TZ6dIju88pp3ovXbYtstvVrn6xFL4sMyeksWV/P2UfQg CVpO/HqRCeSSHqoNJP6vYhKcxAoUETaJ/ehSLa92jiJH6eLTxNCjA0DCF1BCFSKp 2iBFaiaOb/jlEEouPbOX9BwBLVGXHd8ijcLyjV4NOVKsX9+/6l/Mx/HFrtzcoj3f u+v3/duMQvj+zcKpSJtJFUjKRkw//28p59fexjVRqM5AMhcKBSMyebzJAH2dAnWB YYuqkyBQOed6JNfQ1wz2hec0gkJBLz8QO20fMldpjZxEZE96+LNVvhuHlJiOUVDS AVZYNeZPkzUQvoJdh9b+XTqtJEgC1KFlg/ySX3IWEVRd1KOWkoyclVJvEluR+Uvv +Xsv9wxlwBmFkCXIUMq9 =POII -----END PGP SIGNATURE----- Merge tag 'drm-fixes-2021-02-05-1' of git://anongit.freedesktop.org/drm/drm Pull drm fixes from Dave Airlie: "Fixes for rc7, bit bigger than I'd like at this stage, but most of the i915 stuff and some amdgpu is destined for staging and I'd rather not hold it up, the i915 changes also pulled in a few precusor code movement patches to make things cleaner, but nothing seems that horrible, and I've checked over all of it. Otherwise there is a nouveau dma-api warning regression, and a ttm page allocation warning fix, and some fixes for a bridge chip, ttm: - fix huge page warning regression i915: - Skip vswing programming for TBT - Power up combo PHY lanes for HDMI - Fix double YUV range correction on HDR planes - Fix the MST PBN divider calculation - Fix LTTPR vswing/pre-emp setting in non-transparent mode - Move the breadcrumb to the signaler if completed upon cancel - Close race between enable_breadcrumbs and cancel_breadcrumbs - Drop lru bumping on display unpinning amdgpu: - Fix retry in gem create - Vangogh fixes - Fix for display from shared buffers - Various display fixes amdkfd: - Fix regression in buffer free nouveau: - fix DMA API warning regression drm/bridge/lontium-lt9611uxc: - EDID fixes - Don't handle hotplug events in IRQ handler" * tag 'drm-fixes-2021-02-05-1' of git://anongit.freedesktop.org/drm/drm: (29 commits) drm/nouveau: fix dma syncing warning with debugging on. drm/amd/display: Decrement refcount of dc_sink before reassignment drm/amd/display: Free atomic state after drm_atomic_commit drm/amd/display: Fix dc_sink kref count in emulated_link_detect drm/amd/display: Release DSC before acquiring drm/amd/display: Revert "Fix EDID parsing after resume from suspend" drm/amd/display: Add more Clock Sources to DCN2.1 drm/amd/display: reuse current context instead of recreating one drm/amd/display: Fix DPCD translation for LTTPR AUX_RD_INTERVAL drm/amdgpu: enable freesync for A+A configs drm/amd/pm: fill in the data member of v2 gpu metrics table for vangogh drm/amdgpu/gfx10: update CGTS_TCC_DISABLE and CGTS_USER_TCC_DISABLE register offsets for VGH drm/amdkfd: fix null pointer panic while free buffer in kfd drm/amdgpu: fix the issue that retry constantly once the buffer is oversize drm/i915/dp: Fix LTTPR vswing/pre-emp setting in non-transparent mode drm/i915/dp: Move intel_dp_set_signal_levels() to intel_dp_link_training.c drm/i915: Fix the MST PBN divider calculation drm/dp/mst: Export drm_dp_get_vc_payload_bw() drm/i915/gem: Drop lru bumping on display unpinning drm/i915/gt: Close race between enable_breadcrumbs and cancel_breadcrumbs ...
This commit is contained in:
Linus Torvalds
commit
8e91dd934b
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@ -26,6 +26,7 @@
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#include <linux/sched/task.h>
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#include "amdgpu_object.h"
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#include "amdgpu_gem.h"
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#include "amdgpu_vm.h"
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#include "amdgpu_amdkfd.h"
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#include "amdgpu_dma_buf.h"
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@ -1152,7 +1153,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
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struct sg_table *sg = NULL;
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uint64_t user_addr = 0;
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struct amdgpu_bo *bo;
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struct amdgpu_bo_param bp;
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struct drm_gem_object *gobj;
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u32 domain, alloc_domain;
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u64 alloc_flags;
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int ret;
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@ -1220,19 +1221,14 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
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pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s\n",
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va, size, domain_string(alloc_domain));
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memset(&bp, 0, sizeof(bp));
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bp.size = size;
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bp.byte_align = 1;
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bp.domain = alloc_domain;
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bp.flags = alloc_flags;
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bp.type = bo_type;
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bp.resv = NULL;
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ret = amdgpu_bo_create(adev, &bp, &bo);
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ret = amdgpu_gem_object_create(adev, size, 1, alloc_domain, alloc_flags,
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bo_type, NULL, &gobj);
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if (ret) {
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pr_debug("Failed to create BO on domain %s. ret %d\n",
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domain_string(alloc_domain), ret);
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domain_string(alloc_domain), ret);
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goto err_bo_create;
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}
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bo = gem_to_amdgpu_bo(gobj);
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if (bo_type == ttm_bo_type_sg) {
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bo->tbo.sg = sg;
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bo->tbo.ttm->sg = sg;
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@ -926,8 +926,10 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev,
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struct drm_file *file_priv,
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const struct drm_mode_fb_cmd2 *mode_cmd)
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{
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struct drm_gem_object *obj;
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struct amdgpu_framebuffer *amdgpu_fb;
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struct drm_gem_object *obj;
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struct amdgpu_bo *bo;
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uint32_t domains;
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int ret;
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obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
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@ -938,7 +940,9 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev,
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}
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/* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
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if (obj->import_attach) {
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bo = gem_to_amdgpu_bo(obj);
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domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags);
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if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) {
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drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n");
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return ERR_PTR(-EINVAL);
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}
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@ -269,8 +269,8 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
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resv = vm->root.base.bo->tbo.base.resv;
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}
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retry:
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initial_domain = (u32)(0xffffffff & args->in.domains);
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retry:
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r = amdgpu_gem_object_create(adev, size, args->in.alignment,
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initial_domain,
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flags, ttm_bo_type_device, resv, &gobj);
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@ -897,7 +897,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
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return -EINVAL;
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/* A shared bo cannot be migrated to VRAM */
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if (bo->prime_shared_count) {
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if (bo->prime_shared_count || bo->tbo.base.import_attach) {
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if (domain & AMDGPU_GEM_DOMAIN_GTT)
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domain = AMDGPU_GEM_DOMAIN_GTT;
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else
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@ -99,6 +99,10 @@
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#define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580
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#define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0
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#define mmCGTS_TCC_DISABLE_Vangogh 0x5006
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#define mmCGTS_TCC_DISABLE_Vangogh_BASE_IDX 1
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#define mmCGTS_USER_TCC_DISABLE_Vangogh 0x5007
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#define mmCGTS_USER_TCC_DISABLE_Vangogh_BASE_IDX 1
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#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025
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#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1
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#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026
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@ -4936,8 +4940,18 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
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static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
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{
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/* TCCs are global (not instanced). */
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uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
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RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
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uint32_t tcc_disable;
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switch (adev->asic_type) {
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case CHIP_VANGOGH:
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tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_Vangogh) |
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RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_Vangogh);
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break;
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default:
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tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
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RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
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break;
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}
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adev->gfx.config.tcc_disabled_mask =
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REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
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@ -1833,8 +1833,8 @@ static void emulated_link_detect(struct dc_link *link)
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link->type = dc_connection_none;
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prev_sink = link->local_sink;
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if (prev_sink != NULL)
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dc_sink_retain(prev_sink);
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if (prev_sink)
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dc_sink_release(prev_sink);
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switch (link->connector_signal) {
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case SIGNAL_TYPE_HDMI_TYPE_A: {
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@ -1934,7 +1934,7 @@ static void dm_gpureset_commit_state(struct dc_state *dc_state,
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dc_commit_updates_for_stream(
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dm->dc, bundle->surface_updates,
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dc_state->stream_status->plane_count,
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dc_state->streams[k], &bundle->stream_update, dc_state);
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dc_state->streams[k], &bundle->stream_update);
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}
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cleanup:
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@ -1965,8 +1965,7 @@ static void dm_set_dpms_off(struct dc_link *link)
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stream_update.stream = stream_state;
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dc_commit_updates_for_stream(stream_state->ctx->dc, NULL, 0,
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stream_state, &stream_update,
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stream_state->ctx->dc->current_state);
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stream_state, &stream_update);
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mutex_unlock(&adev->dm.dc_lock);
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}
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@ -2330,8 +2329,10 @@ void amdgpu_dm_update_connector_after_detect(
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* TODO: check if we still need the S3 mode update workaround.
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* If yes, put it here.
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*/
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if (aconnector->dc_sink)
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if (aconnector->dc_sink) {
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amdgpu_dm_update_freesync_caps(connector, NULL);
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dc_sink_release(aconnector->dc_sink);
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}
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aconnector->dc_sink = sink;
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dc_sink_retain(aconnector->dc_sink);
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@ -2347,8 +2348,6 @@ void amdgpu_dm_update_connector_after_detect(
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drm_connector_update_edid_property(connector,
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aconnector->edid);
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drm_add_edid_modes(connector, aconnector->edid);
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if (aconnector->dc_link->aux_mode)
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drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
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aconnector->edid);
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@ -7549,7 +7548,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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struct drm_crtc *pcrtc,
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bool wait_for_vblank)
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{
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uint32_t i;
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int i;
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uint64_t timestamp_ns;
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struct drm_plane *plane;
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struct drm_plane_state *old_plane_state, *new_plane_state;
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@ -7590,7 +7589,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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amdgpu_dm_commit_cursors(state);
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/* update planes when needed */
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for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
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for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
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struct drm_crtc *crtc = new_plane_state->crtc;
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struct drm_crtc_state *new_crtc_state;
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struct drm_framebuffer *fb = new_plane_state->fb;
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@ -7813,8 +7812,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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bundle->surface_updates,
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planes_count,
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acrtc_state->stream,
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&bundle->stream_update,
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dc_state);
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&bundle->stream_update);
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/**
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* Enable or disable the interrupts on the backend.
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@ -8150,13 +8148,13 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
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struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
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struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
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struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
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struct dc_surface_update dummy_updates[MAX_SURFACES];
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struct dc_surface_update surface_updates[MAX_SURFACES];
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struct dc_stream_update stream_update;
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struct dc_info_packet hdr_packet;
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struct dc_stream_status *status = NULL;
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bool abm_changed, hdr_changed, scaling_changed;
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memset(&dummy_updates, 0, sizeof(dummy_updates));
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memset(&surface_updates, 0, sizeof(surface_updates));
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memset(&stream_update, 0, sizeof(stream_update));
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if (acrtc) {
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|
|
@ -8213,16 +8211,15 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
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* To fix this, DC should permit updating only stream properties.
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*/
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for (j = 0; j < status->plane_count; j++)
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dummy_updates[j].surface = status->plane_states[0];
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surface_updates[j].surface = status->plane_states[j];
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mutex_lock(&dm->dc_lock);
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dc_commit_updates_for_stream(dm->dc,
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dummy_updates,
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surface_updates,
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status->plane_count,
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dm_new_crtc_state->stream,
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&stream_update,
|
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dc_state);
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&stream_update);
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mutex_unlock(&dm->dc_lock);
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}
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|
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|
|
@ -8359,14 +8356,14 @@ static int dm_force_atomic_commit(struct drm_connector *connector)
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|||
|
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ret = PTR_ERR_OR_ZERO(conn_state);
|
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if (ret)
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goto err;
|
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goto out;
|
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|
||||
/* Attach crtc to drm_atomic_state*/
|
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crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
|
||||
|
||||
ret = PTR_ERR_OR_ZERO(crtc_state);
|
||||
if (ret)
|
||||
goto err;
|
||||
goto out;
|
||||
|
||||
/* force a restore */
|
||||
crtc_state->mode_changed = true;
|
||||
|
|
@ -8376,17 +8373,15 @@ static int dm_force_atomic_commit(struct drm_connector *connector)
|
|||
|
||||
ret = PTR_ERR_OR_ZERO(plane_state);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
goto out;
|
||||
|
||||
/* Call commit internally with the state we just constructed */
|
||||
ret = drm_atomic_commit(state);
|
||||
if (!ret)
|
||||
return 0;
|
||||
|
||||
err:
|
||||
DRM_ERROR("Restoring old state failed with %i\n", ret);
|
||||
out:
|
||||
drm_atomic_state_put(state);
|
||||
if (ret)
|
||||
DRM_ERROR("Restoring old state failed with %i\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -833,6 +833,9 @@ bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
|
|||
if (computed_streams[i])
|
||||
continue;
|
||||
|
||||
if (dcn20_remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)
|
||||
return false;
|
||||
|
||||
mutex_lock(&aconnector->mst_mgr.lock);
|
||||
if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link)) {
|
||||
mutex_unlock(&aconnector->mst_mgr.lock);
|
||||
|
|
@ -850,7 +853,8 @@ bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
|
|||
stream = dc_state->streams[i];
|
||||
|
||||
if (stream->timing.flags.DSC == 1)
|
||||
dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream);
|
||||
if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK)
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
|
|
|
|||
|
|
@ -2679,8 +2679,7 @@ void dc_commit_updates_for_stream(struct dc *dc,
|
|||
struct dc_surface_update *srf_updates,
|
||||
int surface_count,
|
||||
struct dc_stream_state *stream,
|
||||
struct dc_stream_update *stream_update,
|
||||
struct dc_state *state)
|
||||
struct dc_stream_update *stream_update)
|
||||
{
|
||||
const struct dc_stream_status *stream_status;
|
||||
enum surface_update_type update_type;
|
||||
|
|
@ -2699,6 +2698,12 @@ void dc_commit_updates_for_stream(struct dc *dc,
|
|||
|
||||
|
||||
if (update_type >= UPDATE_TYPE_FULL) {
|
||||
struct dc_plane_state *new_planes[MAX_SURFACES];
|
||||
|
||||
memset(new_planes, 0, sizeof(new_planes));
|
||||
|
||||
for (i = 0; i < surface_count; i++)
|
||||
new_planes[i] = srf_updates[i].surface;
|
||||
|
||||
/* initialize scratch memory for building context */
|
||||
context = dc_create_state(dc);
|
||||
|
|
@ -2707,15 +2712,21 @@ void dc_commit_updates_for_stream(struct dc *dc,
|
|||
return;
|
||||
}
|
||||
|
||||
dc_resource_state_copy_construct(state, context);
|
||||
dc_resource_state_copy_construct(
|
||||
dc->current_state, context);
|
||||
|
||||
for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
||||
struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
|
||||
struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
|
||||
|
||||
if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
|
||||
new_pipe->plane_state->force_full_update = true;
|
||||
/*remove old surfaces from context */
|
||||
if (!dc_rem_all_planes_for_stream(dc, stream, context)) {
|
||||
DC_ERROR("Failed to remove streams for new validate context!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* add surface to context */
|
||||
if (!dc_add_all_planes_for_stream(dc, stream, new_planes, surface_count, context)) {
|
||||
DC_ERROR("Failed to add streams for new validate context!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -892,14 +892,14 @@ static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_inte
|
|||
|
||||
switch (dpcd_aux_read_interval) {
|
||||
case 0x01:
|
||||
aux_rd_interval_us = 400;
|
||||
break;
|
||||
case 0x02:
|
||||
aux_rd_interval_us = 4000;
|
||||
break;
|
||||
case 0x03:
|
||||
case 0x02:
|
||||
aux_rd_interval_us = 8000;
|
||||
break;
|
||||
case 0x03:
|
||||
aux_rd_interval_us = 12000;
|
||||
break;
|
||||
case 0x04:
|
||||
aux_rd_interval_us = 16000;
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -283,8 +283,7 @@ void dc_commit_updates_for_stream(struct dc *dc,
|
|||
struct dc_surface_update *srf_updates,
|
||||
int surface_count,
|
||||
struct dc_stream_state *stream,
|
||||
struct dc_stream_update *stream_update,
|
||||
struct dc_state *state);
|
||||
struct dc_stream_update *stream_update);
|
||||
/*
|
||||
* Log the current stream state.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -906,6 +906,8 @@ enum dcn20_clk_src_array_id {
|
|||
DCN20_CLK_SRC_PLL0,
|
||||
DCN20_CLK_SRC_PLL1,
|
||||
DCN20_CLK_SRC_PLL2,
|
||||
DCN20_CLK_SRC_PLL3,
|
||||
DCN20_CLK_SRC_PLL4,
|
||||
DCN20_CLK_SRC_TOTAL_DCN21
|
||||
};
|
||||
|
||||
|
|
@ -2030,6 +2032,14 @@ static bool dcn21_resource_construct(
|
|||
dcn21_clock_source_create(ctx, ctx->dc_bios,
|
||||
CLOCK_SOURCE_COMBO_PHY_PLL2,
|
||||
&clk_src_regs[2], false);
|
||||
pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
|
||||
dcn21_clock_source_create(ctx, ctx->dc_bios,
|
||||
CLOCK_SOURCE_COMBO_PHY_PLL3,
|
||||
&clk_src_regs[3], false);
|
||||
pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
|
||||
dcn21_clock_source_create(ctx, ctx->dc_bios,
|
||||
CLOCK_SOURCE_COMBO_PHY_PLL4,
|
||||
&clk_src_regs[4], false);
|
||||
|
||||
pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
|
||||
|
||||
|
|
|
|||
|
|
@ -591,14 +591,17 @@ static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
|
|||
gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
|
||||
gpu_metrics->average_cpu_power = metrics.Power[0];
|
||||
gpu_metrics->average_soc_power = metrics.Power[1];
|
||||
gpu_metrics->average_gfx_power = metrics.Power[2];
|
||||
memcpy(&gpu_metrics->average_core_power[0],
|
||||
&metrics.CorePower[0],
|
||||
sizeof(uint16_t) * 8);
|
||||
|
||||
gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
|
||||
gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
|
||||
gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
|
||||
gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
|
||||
gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
|
||||
gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
|
||||
|
||||
memcpy(&gpu_metrics->current_coreclk[0],
|
||||
&metrics.CoreFrequency[0],
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
#include <linux/regmap.h>
|
||||
#include <linux/regulator/consumer.h>
|
||||
#include <linux/wait.h>
|
||||
#include <linux/workqueue.h>
|
||||
|
||||
#include <sound/hdmi-codec.h>
|
||||
|
||||
|
|
@ -36,6 +37,7 @@ struct lt9611uxc {
|
|||
struct mutex ocm_lock;
|
||||
|
||||
struct wait_queue_head wq;
|
||||
struct work_struct work;
|
||||
|
||||
struct device_node *dsi0_node;
|
||||
struct device_node *dsi1_node;
|
||||
|
|
@ -52,6 +54,8 @@ struct lt9611uxc {
|
|||
|
||||
bool hpd_supported;
|
||||
bool edid_read;
|
||||
/* can be accessed from different threads, so protect this with ocm_lock */
|
||||
bool hdmi_connected;
|
||||
uint8_t fw_version;
|
||||
};
|
||||
|
||||
|
|
@ -143,21 +147,41 @@ static irqreturn_t lt9611uxc_irq_thread_handler(int irq, void *dev_id)
|
|||
if (irq_status)
|
||||
regmap_write(lt9611uxc->regmap, 0xb022, 0);
|
||||
|
||||
lt9611uxc_unlock(lt9611uxc);
|
||||
|
||||
if (irq_status & BIT(0))
|
||||
if (irq_status & BIT(0)) {
|
||||
lt9611uxc->edid_read = !!(hpd_status & BIT(0));
|
||||
|
||||
if (irq_status & BIT(1)) {
|
||||
if (lt9611uxc->connector.dev)
|
||||
drm_kms_helper_hotplug_event(lt9611uxc->connector.dev);
|
||||
else
|
||||
drm_bridge_hpd_notify(<9611uxc->bridge, !!(hpd_status & BIT(1)));
|
||||
wake_up_all(<9611uxc->wq);
|
||||
}
|
||||
|
||||
if (irq_status & BIT(1)) {
|
||||
lt9611uxc->hdmi_connected = hpd_status & BIT(1);
|
||||
schedule_work(<9611uxc->work);
|
||||
}
|
||||
|
||||
lt9611uxc_unlock(lt9611uxc);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void lt9611uxc_hpd_work(struct work_struct *work)
|
||||
{
|
||||
struct lt9611uxc *lt9611uxc = container_of(work, struct lt9611uxc, work);
|
||||
bool connected;
|
||||
|
||||
if (lt9611uxc->connector.dev)
|
||||
drm_kms_helper_hotplug_event(lt9611uxc->connector.dev);
|
||||
else {
|
||||
|
||||
mutex_lock(<9611uxc->ocm_lock);
|
||||
connected = lt9611uxc->hdmi_connected;
|
||||
mutex_unlock(<9611uxc->ocm_lock);
|
||||
|
||||
drm_bridge_hpd_notify(<9611uxc->bridge,
|
||||
connected ?
|
||||
connector_status_connected :
|
||||
connector_status_disconnected);
|
||||
}
|
||||
}
|
||||
|
||||
static void lt9611uxc_reset(struct lt9611uxc *lt9611uxc)
|
||||
{
|
||||
gpiod_set_value_cansleep(lt9611uxc->reset_gpio, 1);
|
||||
|
|
@ -445,18 +469,21 @@ static enum drm_connector_status lt9611uxc_bridge_detect(struct drm_bridge *brid
|
|||
struct lt9611uxc *lt9611uxc = bridge_to_lt9611uxc(bridge);
|
||||
unsigned int reg_val = 0;
|
||||
int ret;
|
||||
int connected = 1;
|
||||
bool connected = true;
|
||||
|
||||
lt9611uxc_lock(lt9611uxc);
|
||||
|
||||
if (lt9611uxc->hpd_supported) {
|
||||
lt9611uxc_lock(lt9611uxc);
|
||||
ret = regmap_read(lt9611uxc->regmap, 0xb023, ®_val);
|
||||
lt9611uxc_unlock(lt9611uxc);
|
||||
|
||||
if (ret)
|
||||
dev_err(lt9611uxc->dev, "failed to read hpd status: %d\n", ret);
|
||||
else
|
||||
connected = reg_val & BIT(1);
|
||||
}
|
||||
lt9611uxc->hdmi_connected = connected;
|
||||
|
||||
lt9611uxc_unlock(lt9611uxc);
|
||||
|
||||
return connected ? connector_status_connected :
|
||||
connector_status_disconnected;
|
||||
|
|
@ -465,7 +492,7 @@ static enum drm_connector_status lt9611uxc_bridge_detect(struct drm_bridge *brid
|
|||
static int lt9611uxc_wait_for_edid(struct lt9611uxc *lt9611uxc)
|
||||
{
|
||||
return wait_event_interruptible_timeout(lt9611uxc->wq, lt9611uxc->edid_read,
|
||||
msecs_to_jiffies(100));
|
||||
msecs_to_jiffies(500));
|
||||
}
|
||||
|
||||
static int lt9611uxc_get_edid_block(void *data, u8 *buf, unsigned int block, size_t len)
|
||||
|
|
@ -503,7 +530,10 @@ static struct edid *lt9611uxc_bridge_get_edid(struct drm_bridge *bridge,
|
|||
ret = lt9611uxc_wait_for_edid(lt9611uxc);
|
||||
if (ret < 0) {
|
||||
dev_err(lt9611uxc->dev, "wait for EDID failed: %d\n", ret);
|
||||
return ERR_PTR(ret);
|
||||
return NULL;
|
||||
} else if (ret == 0) {
|
||||
dev_err(lt9611uxc->dev, "wait for EDID timeout\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return drm_do_get_edid(connector, lt9611uxc_get_edid_block, lt9611uxc);
|
||||
|
|
@ -926,6 +956,8 @@ static int lt9611uxc_probe(struct i2c_client *client,
|
|||
lt9611uxc->fw_version = ret;
|
||||
|
||||
init_waitqueue_head(<9611uxc->wq);
|
||||
INIT_WORK(<9611uxc->work, lt9611uxc_hpd_work);
|
||||
|
||||
ret = devm_request_threaded_irq(dev, client->irq, NULL,
|
||||
lt9611uxc_irq_thread_handler,
|
||||
IRQF_ONESHOT, "lt9611uxc", lt9611uxc);
|
||||
|
|
@ -962,6 +994,7 @@ static int lt9611uxc_remove(struct i2c_client *client)
|
|||
struct lt9611uxc *lt9611uxc = i2c_get_clientdata(client);
|
||||
|
||||
disable_irq(client->irq);
|
||||
flush_scheduled_work();
|
||||
lt9611uxc_audio_exit(lt9611uxc);
|
||||
drm_bridge_remove(<9611uxc->bridge);
|
||||
|
||||
|
|
|
|||
|
|
@ -3629,14 +3629,26 @@ static int drm_dp_send_up_ack_reply(struct drm_dp_mst_topology_mgr *mgr,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int drm_dp_get_vc_payload_bw(u8 dp_link_bw, u8 dp_link_count)
|
||||
/**
|
||||
* drm_dp_get_vc_payload_bw - get the VC payload BW for an MST link
|
||||
* @link_rate: link rate in 10kbits/s units
|
||||
* @link_lane_count: lane count
|
||||
*
|
||||
* Calculate the total bandwidth of a MultiStream Transport link. The returned
|
||||
* value is in units of PBNs/(timeslots/1 MTP). This value can be used to
|
||||
* convert the number of PBNs required for a given stream to the number of
|
||||
* timeslots this stream requires in each MTP.
|
||||
*/
|
||||
int drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count)
|
||||
{
|
||||
if (dp_link_bw == 0 || dp_link_count == 0)
|
||||
DRM_DEBUG_KMS("invalid link bandwidth in DPCD: %x (link count: %d)\n",
|
||||
dp_link_bw, dp_link_count);
|
||||
if (link_rate == 0 || link_lane_count == 0)
|
||||
DRM_DEBUG_KMS("invalid link rate/lane count: (%d / %d)\n",
|
||||
link_rate, link_lane_count);
|
||||
|
||||
return dp_link_bw * dp_link_count / 2;
|
||||
/* See DP v2.0 2.6.4.2, VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */
|
||||
return link_rate * link_lane_count / 54000;
|
||||
}
|
||||
EXPORT_SYMBOL(drm_dp_get_vc_payload_bw);
|
||||
|
||||
/**
|
||||
* drm_dp_read_mst_cap() - check whether or not a sink supports MST
|
||||
|
|
@ -3692,7 +3704,7 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms
|
|||
goto out_unlock;
|
||||
}
|
||||
|
||||
mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr->dpcd[1],
|
||||
mgr->pbn_div = drm_dp_get_vc_payload_bw(drm_dp_bw_code_to_link_rate(mgr->dpcd[1]),
|
||||
mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK);
|
||||
if (mgr->pbn_div == 0) {
|
||||
ret = -EINVAL;
|
||||
|
|
|
|||
|
|
@ -2754,6 +2754,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
|
|||
int n_entries, ln;
|
||||
u32 val;
|
||||
|
||||
if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)
|
||||
return;
|
||||
|
||||
ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);
|
||||
if (level >= n_entries) {
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
|
|
@ -2890,6 +2893,9 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
|
|||
u32 val, dpcnt_mask, dpcnt_val;
|
||||
int n_entries, ln;
|
||||
|
||||
if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)
|
||||
return;
|
||||
|
||||
ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
|
||||
|
||||
if (level >= n_entries)
|
||||
|
|
@ -3531,6 +3537,23 @@ static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
|
|||
intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
|
||||
}
|
||||
|
||||
static void intel_ddi_power_up_lanes(struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
||||
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
|
||||
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
||||
|
||||
if (intel_phy_is_combo(i915, phy)) {
|
||||
bool lane_reversal =
|
||||
dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
|
||||
|
||||
intel_combo_phy_power_up_lanes(i915, phy, false,
|
||||
crtc_state->lane_count,
|
||||
lane_reversal);
|
||||
}
|
||||
}
|
||||
|
||||
static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
|
||||
struct intel_encoder *encoder,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
|
|
@ -3620,14 +3643,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
|
|||
* 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
|
||||
* the used lanes of the DDI.
|
||||
*/
|
||||
if (intel_phy_is_combo(dev_priv, phy)) {
|
||||
bool lane_reversal =
|
||||
dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
|
||||
|
||||
intel_combo_phy_power_up_lanes(dev_priv, phy, false,
|
||||
crtc_state->lane_count,
|
||||
lane_reversal);
|
||||
}
|
||||
intel_ddi_power_up_lanes(encoder, crtc_state);
|
||||
|
||||
/*
|
||||
* 7.g Configure and enable DDI_BUF_CTL
|
||||
|
|
@ -3712,14 +3728,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
|
|||
else
|
||||
intel_prepare_dp_ddi_buffers(encoder, crtc_state);
|
||||
|
||||
if (intel_phy_is_combo(dev_priv, phy)) {
|
||||
bool lane_reversal =
|
||||
dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
|
||||
|
||||
intel_combo_phy_power_up_lanes(dev_priv, phy, false,
|
||||
crtc_state->lane_count,
|
||||
lane_reversal);
|
||||
}
|
||||
intel_ddi_power_up_lanes(encoder, crtc_state);
|
||||
|
||||
intel_ddi_init_dp_buf_reg(encoder, crtc_state);
|
||||
if (!is_mst)
|
||||
|
|
@ -4205,6 +4214,8 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
|
|||
intel_de_write(dev_priv, reg, val);
|
||||
}
|
||||
|
||||
intel_ddi_power_up_lanes(encoder, crtc_state);
|
||||
|
||||
/* In HDMI/DVI mode, the port width, and swing/emphasis values
|
||||
* are ignored so nothing special needs to be done besides
|
||||
* enabling the port.
|
||||
|
|
|
|||
|
|
@ -2309,7 +2309,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
|
|||
*/
|
||||
ret = i915_vma_pin_fence(vma);
|
||||
if (ret != 0 && INTEL_GEN(dev_priv) < 4) {
|
||||
i915_gem_object_unpin_from_display_plane(vma);
|
||||
i915_vma_unpin(vma);
|
||||
vma = ERR_PTR(ret);
|
||||
goto err;
|
||||
}
|
||||
|
|
@ -2327,12 +2327,9 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
|
|||
|
||||
void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
|
||||
{
|
||||
i915_gem_object_lock(vma->obj, NULL);
|
||||
if (flags & PLANE_HAS_FENCE)
|
||||
i915_vma_unpin_fence(vma);
|
||||
i915_gem_object_unpin_from_display_plane(vma);
|
||||
i915_gem_object_unlock(vma->obj);
|
||||
|
||||
i915_vma_unpin(vma);
|
||||
i915_vma_put(vma);
|
||||
}
|
||||
|
||||
|
|
@ -4807,6 +4804,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
|
|||
plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
|
||||
} else if (fb->format->is_yuv) {
|
||||
plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
|
||||
if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
|
||||
plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
|
||||
}
|
||||
|
||||
return plane_color_ctl;
|
||||
|
|
|
|||
|
|
@ -4637,24 +4637,6 @@ ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
|
|||
intel_de_posting_read(dev_priv, intel_dp->output_reg);
|
||||
}
|
||||
|
||||
void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
|
||||
const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
||||
u8 train_set = intel_dp->train_set[0];
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
|
||||
train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
|
||||
train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
|
||||
drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
|
||||
(train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
|
||||
DP_TRAIN_PRE_EMPHASIS_SHIFT,
|
||||
train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
|
||||
" (max)" : "");
|
||||
|
||||
intel_dp->set_signal_levels(intel_dp, crtc_state);
|
||||
}
|
||||
|
||||
void
|
||||
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
|
|
@ -5703,7 +5685,7 @@ static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
|
|||
|
||||
intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
|
||||
|
||||
intel_dp_set_signal_levels(intel_dp, crtc_state);
|
||||
intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
|
||||
|
||||
intel_dp_phy_pattern_update(intel_dp, crtc_state);
|
||||
|
||||
|
|
|
|||
|
|
@ -96,9 +96,6 @@ void
|
|||
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
u8 dp_train_pat);
|
||||
void
|
||||
intel_dp_set_signal_levels(struct intel_dp *intel_dp,
|
||||
const struct intel_crtc_state *crtc_state);
|
||||
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
|
||||
u8 *link_bw, u8 *rate_select);
|
||||
bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
|
||||
|
|
|
|||
|
|
@ -334,6 +334,27 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
|
|||
return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;
|
||||
}
|
||||
|
||||
void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
enum drm_dp_phy dp_phy)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
||||
u8 train_set = intel_dp->train_set[0];
|
||||
char phy_name[10];
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s, pre-emphasis level %d%s, at %s\n",
|
||||
train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
|
||||
train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "",
|
||||
(train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
|
||||
DP_TRAIN_PRE_EMPHASIS_SHIFT,
|
||||
train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
|
||||
" (max)" : "",
|
||||
intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
|
||||
|
||||
if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
|
||||
intel_dp->set_signal_levels(intel_dp, crtc_state);
|
||||
}
|
||||
|
||||
static bool
|
||||
intel_dp_reset_link_train(struct intel_dp *intel_dp,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
|
|
@ -341,7 +362,7 @@ intel_dp_reset_link_train(struct intel_dp *intel_dp,
|
|||
u8 dp_train_pat)
|
||||
{
|
||||
memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
|
||||
intel_dp_set_signal_levels(intel_dp, crtc_state);
|
||||
intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
|
||||
return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat);
|
||||
}
|
||||
|
||||
|
|
@ -355,7 +376,7 @@ intel_dp_update_link_train(struct intel_dp *intel_dp,
|
|||
DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy);
|
||||
int ret;
|
||||
|
||||
intel_dp_set_signal_levels(intel_dp, crtc_state);
|
||||
intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
|
||||
|
||||
ret = drm_dp_dpcd_write(&intel_dp->aux, reg,
|
||||
intel_dp->train_set, crtc_state->lane_count);
|
||||
|
|
|
|||
|
|
@ -17,6 +17,9 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
|
|||
const struct intel_crtc_state *crtc_state,
|
||||
enum drm_dp_phy dp_phy,
|
||||
const u8 link_status[DP_LINK_STATUS_SIZE]);
|
||||
void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
enum drm_dp_phy dp_phy);
|
||||
void intel_dp_start_link_train(struct intel_dp *intel_dp,
|
||||
const struct intel_crtc_state *crtc_state);
|
||||
void intel_dp_stop_link_train(struct intel_dp *intel_dp,
|
||||
|
|
|
|||
|
|
@ -69,7 +69,9 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
|
|||
|
||||
slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr,
|
||||
connector->port,
|
||||
crtc_state->pbn, 0);
|
||||
crtc_state->pbn,
|
||||
drm_dp_get_vc_payload_bw(crtc_state->port_clock,
|
||||
crtc_state->lane_count));
|
||||
if (slots == -EDEADLK)
|
||||
return slots;
|
||||
if (slots >= 0)
|
||||
|
|
|
|||
|
|
@ -359,7 +359,7 @@ static void intel_overlay_release_old_vma(struct intel_overlay *overlay)
|
|||
intel_frontbuffer_flip_complete(overlay->i915,
|
||||
INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
|
||||
|
||||
i915_gem_object_unpin_from_display_plane(vma);
|
||||
i915_vma_unpin(vma);
|
||||
i915_vma_put(vma);
|
||||
}
|
||||
|
||||
|
|
@ -860,7 +860,7 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay,
|
|||
return 0;
|
||||
|
||||
out_unpin:
|
||||
i915_gem_object_unpin_from_display_plane(vma);
|
||||
i915_vma_unpin(vma);
|
||||
out_pin_section:
|
||||
atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
|
||||
|
||||
|
|
|
|||
|
|
@ -618,13 +618,19 @@ skl_program_scaler(struct intel_plane *plane,
|
|||
|
||||
/* Preoffset values for YUV to RGB Conversion */
|
||||
#define PREOFF_YUV_TO_RGB_HI 0x1800
|
||||
#define PREOFF_YUV_TO_RGB_ME 0x1F00
|
||||
#define PREOFF_YUV_TO_RGB_ME 0x0000
|
||||
#define PREOFF_YUV_TO_RGB_LO 0x1800
|
||||
|
||||
#define ROFF(x) (((x) & 0xffff) << 16)
|
||||
#define GOFF(x) (((x) & 0xffff) << 0)
|
||||
#define BOFF(x) (((x) & 0xffff) << 16)
|
||||
|
||||
/*
|
||||
* Programs the input color space conversion stage for ICL HDR planes.
|
||||
* Note that it is assumed that this stage always happens after YUV
|
||||
* range correction. Thus, the input to this stage is assumed to be
|
||||
* in full-range YCbCr.
|
||||
*/
|
||||
static void
|
||||
icl_program_input_csc(struct intel_plane *plane,
|
||||
const struct intel_crtc_state *crtc_state,
|
||||
|
|
@ -672,52 +678,7 @@ icl_program_input_csc(struct intel_plane *plane,
|
|||
0x0, 0x7800, 0x7F10,
|
||||
},
|
||||
};
|
||||
|
||||
/* Matrix for Limited Range to Full Range Conversion */
|
||||
static const u16 input_csc_matrix_lr[][9] = {
|
||||
/*
|
||||
* BT.601 Limted range YCbCr -> full range RGB
|
||||
* The matrix required is :
|
||||
* [1.164384, 0.000, 1.596027,
|
||||
* 1.164384, -0.39175, -0.812813,
|
||||
* 1.164384, 2.017232, 0.0000]
|
||||
*/
|
||||
[DRM_COLOR_YCBCR_BT601] = {
|
||||
0x7CC8, 0x7950, 0x0,
|
||||
0x8D00, 0x7950, 0x9C88,
|
||||
0x0, 0x7950, 0x6810,
|
||||
},
|
||||
/*
|
||||
* BT.709 Limited range YCbCr -> full range RGB
|
||||
* The matrix required is :
|
||||
* [1.164384, 0.000, 1.792741,
|
||||
* 1.164384, -0.213249, -0.532909,
|
||||
* 1.164384, 2.112402, 0.0000]
|
||||
*/
|
||||
[DRM_COLOR_YCBCR_BT709] = {
|
||||
0x7E58, 0x7950, 0x0,
|
||||
0x8888, 0x7950, 0xADA8,
|
||||
0x0, 0x7950, 0x6870,
|
||||
},
|
||||
/*
|
||||
* BT.2020 Limited range YCbCr -> full range RGB
|
||||
* The matrix required is :
|
||||
* [1.164, 0.000, 1.678,
|
||||
* 1.164, -0.1873, -0.6504,
|
||||
* 1.164, 2.1417, 0.0000]
|
||||
*/
|
||||
[DRM_COLOR_YCBCR_BT2020] = {
|
||||
0x7D70, 0x7950, 0x0,
|
||||
0x8A68, 0x7950, 0xAC00,
|
||||
0x0, 0x7950, 0x6890,
|
||||
},
|
||||
};
|
||||
const u16 *csc;
|
||||
|
||||
if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
|
||||
csc = input_csc_matrix[plane_state->hw.color_encoding];
|
||||
else
|
||||
csc = input_csc_matrix_lr[plane_state->hw.color_encoding];
|
||||
const u16 *csc = input_csc_matrix[plane_state->hw.color_encoding];
|
||||
|
||||
intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0),
|
||||
ROFF(csc[0]) | GOFF(csc[1]));
|
||||
|
|
@ -734,14 +695,8 @@ icl_program_input_csc(struct intel_plane *plane,
|
|||
|
||||
intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),
|
||||
PREOFF_YUV_TO_RGB_HI);
|
||||
if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
|
||||
intel_de_write_fw(dev_priv,
|
||||
PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
|
||||
0);
|
||||
else
|
||||
intel_de_write_fw(dev_priv,
|
||||
PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
|
||||
PREOFF_YUV_TO_RGB_ME);
|
||||
intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
|
||||
PREOFF_YUV_TO_RGB_ME);
|
||||
intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),
|
||||
PREOFF_YUV_TO_RGB_LO);
|
||||
intel_de_write_fw(dev_priv,
|
||||
|
|
|
|||
|
|
@ -387,48 +387,6 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
|
|||
return vma;
|
||||
}
|
||||
|
||||
static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(obj->base.dev);
|
||||
struct i915_vma *vma;
|
||||
|
||||
if (list_empty(&obj->vma.list))
|
||||
return;
|
||||
|
||||
mutex_lock(&i915->ggtt.vm.mutex);
|
||||
spin_lock(&obj->vma.lock);
|
||||
for_each_ggtt_vma(vma, obj) {
|
||||
if (!drm_mm_node_allocated(&vma->node))
|
||||
continue;
|
||||
|
||||
GEM_BUG_ON(vma->vm != &i915->ggtt.vm);
|
||||
list_move_tail(&vma->vm_link, &vma->vm->bound_list);
|
||||
}
|
||||
spin_unlock(&obj->vma.lock);
|
||||
mutex_unlock(&i915->ggtt.vm.mutex);
|
||||
|
||||
if (i915_gem_object_is_shrinkable(obj)) {
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&i915->mm.obj_lock, flags);
|
||||
|
||||
if (obj->mm.madv == I915_MADV_WILLNEED &&
|
||||
!atomic_read(&obj->mm.shrink_pin))
|
||||
list_move_tail(&obj->mm.link, &i915->mm.shrink_list);
|
||||
|
||||
spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
i915_gem_object_unpin_from_display_plane(struct i915_vma *vma)
|
||||
{
|
||||
/* Bump the LRU to try and avoid premature eviction whilst flipping */
|
||||
i915_gem_object_bump_inactive_ggtt(vma->obj);
|
||||
|
||||
i915_vma_unpin(vma);
|
||||
}
|
||||
|
||||
/**
|
||||
* Moves a single object to the CPU read, and possibly write domain.
|
||||
* @obj: object to act on
|
||||
|
|
@ -569,9 +527,6 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
|
|||
else
|
||||
err = i915_gem_object_set_to_cpu_domain(obj, write_domain);
|
||||
|
||||
/* And bump the LRU for this access */
|
||||
i915_gem_object_bump_inactive_ggtt(obj);
|
||||
|
||||
i915_gem_object_unlock(obj);
|
||||
|
||||
if (write_domain)
|
||||
|
|
|
|||
|
|
@ -486,7 +486,6 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
|
|||
u32 alignment,
|
||||
const struct i915_ggtt_view *view,
|
||||
unsigned int flags);
|
||||
void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
|
||||
|
||||
void i915_gem_object_make_unshrinkable(struct drm_i915_gem_object *obj);
|
||||
void i915_gem_object_make_shrinkable(struct drm_i915_gem_object *obj);
|
||||
|
|
|
|||
|
|
@ -187,18 +187,6 @@ static void add_retire(struct intel_breadcrumbs *b, struct intel_timeline *tl)
|
|||
intel_engine_add_retire(b->irq_engine, tl);
|
||||
}
|
||||
|
||||
static bool __signal_request(struct i915_request *rq)
|
||||
{
|
||||
GEM_BUG_ON(test_bit(I915_FENCE_FLAG_SIGNAL, &rq->fence.flags));
|
||||
|
||||
if (!__dma_fence_signal(&rq->fence)) {
|
||||
i915_request_put(rq);
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static struct llist_node *
|
||||
slist_add(struct llist_node *node, struct llist_node *head)
|
||||
{
|
||||
|
|
@ -269,9 +257,11 @@ static void signal_irq_work(struct irq_work *work)
|
|||
release = remove_signaling_context(b, ce);
|
||||
spin_unlock(&ce->signal_lock);
|
||||
|
||||
if (__signal_request(rq))
|
||||
if (__dma_fence_signal(&rq->fence))
|
||||
/* We own signal_node now, xfer to local list */
|
||||
signal = slist_add(&rq->signal_node, signal);
|
||||
else
|
||||
i915_request_put(rq);
|
||||
|
||||
if (release) {
|
||||
add_retire(b, ce->timeline);
|
||||
|
|
@ -358,6 +348,17 @@ void intel_breadcrumbs_free(struct intel_breadcrumbs *b)
|
|||
kfree(b);
|
||||
}
|
||||
|
||||
static void irq_signal_request(struct i915_request *rq,
|
||||
struct intel_breadcrumbs *b)
|
||||
{
|
||||
if (!__dma_fence_signal(&rq->fence))
|
||||
return;
|
||||
|
||||
i915_request_get(rq);
|
||||
if (llist_add(&rq->signal_node, &b->signaled_requests))
|
||||
irq_work_queue(&b->irq_work);
|
||||
}
|
||||
|
||||
static void insert_breadcrumb(struct i915_request *rq)
|
||||
{
|
||||
struct intel_breadcrumbs *b = READ_ONCE(rq->engine)->breadcrumbs;
|
||||
|
|
@ -367,17 +368,13 @@ static void insert_breadcrumb(struct i915_request *rq)
|
|||
if (test_bit(I915_FENCE_FLAG_SIGNAL, &rq->fence.flags))
|
||||
return;
|
||||
|
||||
i915_request_get(rq);
|
||||
|
||||
/*
|
||||
* If the request is already completed, we can transfer it
|
||||
* straight onto a signaled list, and queue the irq worker for
|
||||
* its signal completion.
|
||||
*/
|
||||
if (__i915_request_is_complete(rq)) {
|
||||
if (__signal_request(rq) &&
|
||||
llist_add(&rq->signal_node, &b->signaled_requests))
|
||||
irq_work_queue(&b->irq_work);
|
||||
irq_signal_request(rq, b);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -408,6 +405,8 @@ static void insert_breadcrumb(struct i915_request *rq)
|
|||
break;
|
||||
}
|
||||
}
|
||||
|
||||
i915_request_get(rq);
|
||||
list_add_rcu(&rq->signal_link, pos);
|
||||
GEM_BUG_ON(!check_signal_order(ce, rq));
|
||||
GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags));
|
||||
|
|
@ -448,19 +447,25 @@ bool i915_request_enable_breadcrumb(struct i915_request *rq)
|
|||
|
||||
void i915_request_cancel_breadcrumb(struct i915_request *rq)
|
||||
{
|
||||
struct intel_breadcrumbs *b = READ_ONCE(rq->engine)->breadcrumbs;
|
||||
struct intel_context *ce = rq->context;
|
||||
bool release;
|
||||
|
||||
if (!test_and_clear_bit(I915_FENCE_FLAG_SIGNAL, &rq->fence.flags))
|
||||
return;
|
||||
|
||||
spin_lock(&ce->signal_lock);
|
||||
if (!test_and_clear_bit(I915_FENCE_FLAG_SIGNAL, &rq->fence.flags)) {
|
||||
spin_unlock(&ce->signal_lock);
|
||||
return;
|
||||
}
|
||||
|
||||
list_del_rcu(&rq->signal_link);
|
||||
release = remove_signaling_context(rq->engine->breadcrumbs, ce);
|
||||
release = remove_signaling_context(b, ce);
|
||||
spin_unlock(&ce->signal_lock);
|
||||
if (release)
|
||||
intel_context_put(ce);
|
||||
|
||||
if (__i915_request_is_complete(rq))
|
||||
irq_signal_request(rq, b);
|
||||
|
||||
i915_request_put(rq);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -547,7 +547,7 @@ nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
|
|||
{
|
||||
struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
|
||||
struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
|
||||
int i;
|
||||
int i, j;
|
||||
|
||||
if (!ttm_dma)
|
||||
return;
|
||||
|
|
@ -556,10 +556,21 @@ nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
|
|||
if (nvbo->force_coherent)
|
||||
return;
|
||||
|
||||
for (i = 0; i < ttm_dma->num_pages; i++)
|
||||
for (i = 0; i < ttm_dma->num_pages; ++i) {
|
||||
struct page *p = ttm_dma->pages[i];
|
||||
size_t num_pages = 1;
|
||||
|
||||
for (j = i + 1; j < ttm_dma->num_pages; ++j) {
|
||||
if (++p != ttm_dma->pages[j])
|
||||
break;
|
||||
|
||||
++num_pages;
|
||||
}
|
||||
dma_sync_single_for_device(drm->dev->dev,
|
||||
ttm_dma->dma_address[i],
|
||||
PAGE_SIZE, DMA_TO_DEVICE);
|
||||
num_pages * PAGE_SIZE, DMA_TO_DEVICE);
|
||||
i += num_pages;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -567,7 +578,7 @@ nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
|
|||
{
|
||||
struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
|
||||
struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
|
||||
int i;
|
||||
int i, j;
|
||||
|
||||
if (!ttm_dma)
|
||||
return;
|
||||
|
|
@ -576,9 +587,21 @@ nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
|
|||
if (nvbo->force_coherent)
|
||||
return;
|
||||
|
||||
for (i = 0; i < ttm_dma->num_pages; i++)
|
||||
for (i = 0; i < ttm_dma->num_pages; ++i) {
|
||||
struct page *p = ttm_dma->pages[i];
|
||||
size_t num_pages = 1;
|
||||
|
||||
for (j = i + 1; j < ttm_dma->num_pages; ++j) {
|
||||
if (++p != ttm_dma->pages[j])
|
||||
break;
|
||||
|
||||
++num_pages;
|
||||
}
|
||||
|
||||
dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i],
|
||||
PAGE_SIZE, DMA_FROM_DEVICE);
|
||||
num_pages * PAGE_SIZE, DMA_FROM_DEVICE);
|
||||
i += num_pages;
|
||||
}
|
||||
}
|
||||
|
||||
void nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object *bo)
|
||||
|
|
|
|||
|
|
@ -84,7 +84,7 @@ static struct page *ttm_pool_alloc_page(struct ttm_pool *pool, gfp_t gfp_flags,
|
|||
* put_page() on a TTM allocated page is illegal.
|
||||
*/
|
||||
if (order)
|
||||
gfp_flags |= __GFP_NOMEMALLOC | __GFP_NORETRY |
|
||||
gfp_flags |= __GFP_NOMEMALLOC | __GFP_NORETRY | __GFP_NOWARN |
|
||||
__GFP_KSWAPD_RECLAIM;
|
||||
|
||||
if (!pool->use_dma_alloc) {
|
||||
|
|
|
|||
|
|
@ -783,6 +783,7 @@ drm_dp_mst_detect_port(struct drm_connector *connector,
|
|||
|
||||
struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port);
|
||||
|
||||
int drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count);
|
||||
|
||||
int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue