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https://github.com/torvalds/linux
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MIPS: Convert R4600_V1_HIT_CACHEOP into a config option
Use a new config option to enable R4600 V1 cacheop hit workaround and remove define from the different war.h files. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
parent
802b83627f
commit
5e5b652712
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@ -639,6 +639,7 @@ config SGI_IP22
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select SYS_SUPPORTS_64BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_SUPPORTS_BIG_ENDIAN
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select WAR_R4600_V1_INDEX_ICACHEOP
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select WAR_R4600_V1_INDEX_ICACHEOP
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select WAR_R4600_V1_HIT_CACHEOP
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select MIPS_L1_CACHE_SHIFT_7
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select MIPS_L1_CACHE_SHIFT_7
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help
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help
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This are the SGI Indy, Challenge S and Indigo2, as well as certain
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This are the SGI Indy, Challenge S and Indigo2, as well as certain
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@ -2615,6 +2616,33 @@ config MIPS_CRC_SUPPORT
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config WAR_R4600_V1_INDEX_ICACHEOP
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config WAR_R4600_V1_INDEX_ICACHEOP
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bool
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bool
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# Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
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#
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# 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
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# Hit_Invalidate_D and Create_Dirty_Excl_D should only be
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# executed if there is no other dcache activity. If the dcache is
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# accessed for another instruction immeidately preceding when these
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# cache instructions are executing, it is possible that the dcache
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# tag match outputs used by these cache instructions will be
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# incorrect. These cache instructions should be preceded by at least
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# four instructions that are not any kind of load or store
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# instruction.
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#
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# This is not allowed: lw
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# nop
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# nop
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# nop
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# cache Hit_Writeback_Invalidate_D
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#
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# This is allowed: lw
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# nop
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# nop
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# nop
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# nop
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# cache Hit_Writeback_Invalidate_D
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config WAR_R4600_V1_HIT_CACHEOP
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bool
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#
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#
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# - Highmem only makes sense for the 32-bit kernel.
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# - Highmem only makes sense for the 32-bit kernel.
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# - The current highmem code will only work properly on physically indexed
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# - The current highmem code will only work properly on physically indexed
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@ -9,7 +9,6 @@
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#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
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#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
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#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
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#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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@ -8,7 +8,6 @@
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#ifndef __ASM_MACH_GENERIC_WAR_H
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#ifndef __ASM_MACH_GENERIC_WAR_H
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#define __ASM_MACH_GENERIC_WAR_H
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#define __ASM_MACH_GENERIC_WAR_H
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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@ -12,7 +12,6 @@
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* R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
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* R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
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*/
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*/
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#define R4600_V1_HIT_CACHEOP_WAR 1
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#define R4600_V2_HIT_CACHEOP_WAR 1
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#define R4600_V2_HIT_CACHEOP_WAR 1
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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@ -8,7 +8,6 @@
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#ifndef __ASM_MIPS_MACH_IP27_WAR_H
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#ifndef __ASM_MIPS_MACH_IP27_WAR_H
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#define __ASM_MIPS_MACH_IP27_WAR_H
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#define __ASM_MIPS_MACH_IP27_WAR_H
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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@ -8,7 +8,6 @@
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#ifndef __ASM_MIPS_MACH_IP28_WAR_H
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#ifndef __ASM_MIPS_MACH_IP28_WAR_H
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#define __ASM_MIPS_MACH_IP28_WAR_H
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#define __ASM_MIPS_MACH_IP28_WAR_H
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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@ -5,7 +5,6 @@
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#ifndef __ASM_MIPS_MACH_IP30_WAR_H
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#ifndef __ASM_MIPS_MACH_IP30_WAR_H
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#define __ASM_MIPS_MACH_IP30_WAR_H
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#define __ASM_MIPS_MACH_IP30_WAR_H
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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@ -8,7 +8,6 @@
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#ifndef __ASM_MIPS_MACH_IP32_WAR_H
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#ifndef __ASM_MIPS_MACH_IP32_WAR_H
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#define __ASM_MIPS_MACH_IP32_WAR_H
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#define __ASM_MIPS_MACH_IP32_WAR_H
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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@ -8,7 +8,6 @@
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#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
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#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
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#define __ASM_MIPS_MACH_MIPS_WAR_H
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#define __ASM_MIPS_MACH_MIPS_WAR_H
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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@ -8,7 +8,6 @@
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#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
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#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
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#define __ASM_MIPS_MACH_MIPS_WAR_H
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#define __ASM_MIPS_MACH_MIPS_WAR_H
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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@ -12,7 +12,6 @@
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* The RM200C seems to have been shipped only with V2.0 R4600s
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* The RM200C seems to have been shipped only with V2.0 R4600s
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*/
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*/
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 1
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#define R4600_V2_HIT_CACHEOP_WAR 1
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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@ -8,7 +8,6 @@
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#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
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#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
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#define __ASM_MIPS_MACH_SIBYTE_WAR_H
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#define __ASM_MIPS_MACH_SIBYTE_WAR_H
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#if defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
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#if defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
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@ -8,7 +8,6 @@
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#ifndef __ASM_MIPS_MACH_TX49XX_WAR_H
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#ifndef __ASM_MIPS_MACH_TX49XX_WAR_H
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#define __ASM_MIPS_MACH_TX49XX_WAR_H
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#define __ASM_MIPS_MACH_TX49XX_WAR_H
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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@ -72,37 +72,6 @@
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#define DADDI_WAR 0
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#define DADDI_WAR 0
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#endif
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#endif
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/*
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* Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
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*
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* 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
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* Hit_Invalidate_D and Create_Dirty_Excl_D should only be
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* executed if there is no other dcache activity. If the dcache is
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* accessed for another instruction immeidately preceding when these
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* cache instructions are executing, it is possible that the dcache
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* tag match outputs used by these cache instructions will be
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* incorrect. These cache instructions should be preceded by at least
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* four instructions that are not any kind of load or store
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* instruction.
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*
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* This is not allowed: lw
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* nop
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* nop
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* nop
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* cache Hit_Writeback_Invalidate_D
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*
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* This is allowed: lw
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* nop
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* nop
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* nop
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* nop
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* cache Hit_Writeback_Invalidate_D
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*/
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#ifndef R4600_V1_HIT_CACHEOP_WAR
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#error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform
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#endif
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/*
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/*
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* Writeback and invalidate the primary cache dcache before DMA.
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* Writeback and invalidate the primary cache dcache before DMA.
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*
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*
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@ -132,7 +132,7 @@ struct bcache_ops *bcops = &no_sc_ops;
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do { \
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do { \
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if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
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if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
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*(volatile unsigned long *)CKSEG1; \
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*(volatile unsigned long *)CKSEG1; \
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if (R4600_V1_HIT_CACHEOP_WAR) \
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if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP)) \
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__asm__ __volatile__("nop;nop;nop;nop"); \
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__asm__ __volatile__("nop;nop;nop;nop"); \
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} while (0)
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} while (0)
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@ -250,7 +250,8 @@ static inline void build_clear_pref(u32 **buf, int off)
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if (cpu_has_cache_cdex_s) {
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if (cpu_has_cache_cdex_s) {
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uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
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uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
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} else if (cpu_has_cache_cdex_p) {
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} else if (cpu_has_cache_cdex_p) {
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if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
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if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP) &&
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cpu_is_r4600_v1_x()) {
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uasm_i_nop(buf);
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uasm_i_nop(buf);
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uasm_i_nop(buf);
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uasm_i_nop(buf);
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uasm_i_nop(buf);
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uasm_i_nop(buf);
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@ -402,7 +403,8 @@ static inline void build_copy_store_pref(u32 **buf, int off)
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if (cpu_has_cache_cdex_s) {
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if (cpu_has_cache_cdex_s) {
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uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
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uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
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} else if (cpu_has_cache_cdex_p) {
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} else if (cpu_has_cache_cdex_p) {
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if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
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if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP) &&
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cpu_is_r4600_v1_x()) {
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uasm_i_nop(buf);
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uasm_i_nop(buf);
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uasm_i_nop(buf);
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uasm_i_nop(buf);
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uasm_i_nop(buf);
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uasm_i_nop(buf);
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