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MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config option

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Use a new config option to enable R4600 V1 index I-cacheop workaround
and remove define from different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Thomas Bogendoerfer 2020-08-24 18:32:43 +02:00
parent 8c2ede45ed
commit 802b83627f
15 changed files with 12 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
arch/mips/Kconfig
View File

@ -638,6 +638,7 @@ config SGI_IP22
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select WAR_R4600_V1_INDEX_ICACHEOP
select MIPS_L1_CACHE_SHIFT_7
help
This are the SGI Indy, Challenge S and Indigo2, as well as certain
@ -2607,6 +2608,13 @@ config MIPS_ASID_BITS_VARIABLE
config MIPS_CRC_SUPPORT
bool
# R4600 erratum. Due to the lack of errata information the exact
# technical details aren't known. I've experimentally found that disabling
# interrupts during indexed I-cache flushes seems to be sufficient to deal
# with the issue.
config WAR_R4600_V1_INDEX_ICACHEOP
bool
#
# - Highmem only makes sense for the 32-bit kernel.
# - The current highmem code will only work properly on physically indexed

1
arch/mips/include/asm/mach-cavium-octeon/war.h
View File

@ -9,7 +9,6 @@
#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0

1
arch/mips/include/asm/mach-generic/war.h
View File

@ -8,7 +8,6 @@
#ifndef __ASM_MACH_GENERIC_WAR_H
#define __ASM_MACH_GENERIC_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0

1
arch/mips/include/asm/mach-ip22/war.h
View File

@ -12,7 +12,6 @@
* R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
*/
#define R4600_V1_INDEX_ICACHEOP_WAR 1
#define R4600_V1_HIT_CACHEOP_WAR 1
#define R4600_V2_HIT_CACHEOP_WAR 1
#define BCM1250_M3_WAR 0

1
arch/mips/include/asm/mach-ip27/war.h
View File

@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_IP27_WAR_H
#define __ASM_MIPS_MACH_IP27_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0

1
arch/mips/include/asm/mach-ip28/war.h
View File

@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_IP28_WAR_H
#define __ASM_MIPS_MACH_IP28_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0

1
arch/mips/include/asm/mach-ip30/war.h
View File

@ -5,7 +5,6 @@
#ifndef __ASM_MIPS_MACH_IP30_WAR_H
#define __ASM_MIPS_MACH_IP30_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0

1
arch/mips/include/asm/mach-ip32/war.h
View File

@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_IP32_WAR_H
#define __ASM_MIPS_MACH_IP32_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0

1
arch/mips/include/asm/mach-malta/war.h
View File

@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
#define __ASM_MIPS_MACH_MIPS_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0

1
arch/mips/include/asm/mach-rc32434/war.h
View File

@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
#define __ASM_MIPS_MACH_MIPS_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0

1
arch/mips/include/asm/mach-rm/war.h
View File

@ -12,7 +12,6 @@
* The RM200C seems to have been shipped only with V2.0 R4600s
*/
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 1
#define BCM1250_M3_WAR 0

1
arch/mips/include/asm/mach-sibyte/war.h
View File

@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
#define __ASM_MIPS_MACH_SIBYTE_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0

1
arch/mips/include/asm/mach-tx49xx/war.h
View File

@ -8,7 +8,6 @@
#ifndef __ASM_MIPS_MACH_TX49XX_WAR_H
#define __ASM_MIPS_MACH_TX49XX_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0

10
arch/mips/include/asm/war.h
View File

@ -72,16 +72,6 @@
#define DADDI_WAR 0
#endif
/*
* Another R4600 erratum. Due to the lack of errata information the exact
* technical details aren't known. I've experimentally found that disabling
* interrupts during indexed I-cache flushes seems to be sufficient to deal
* with the issue.
*/
#ifndef R4600_V1_INDEX_ICACHEOP_WAR
#error Check setting of R4600_V1_INDEX_ICACHEOP_WAR for your platform
#endif
/*
* Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
*

6
arch/mips/mm/c-r4k.c
View File

@ -366,7 +366,8 @@ static void r4k_blast_icache_page_indexed_setup(void)
else if (ic_lsize == 16)
r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
else if (ic_lsize == 32) {
if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) &&
cpu_is_r4600_v1_x())
r4k_blast_icache_page_indexed =
blast_icache32_r4600_v1_page_indexed;
else if (TX49XX_ICACHE_INDEX_INV_WAR)
@ -394,7 +395,8 @@ static void r4k_blast_icache_setup(void)
else if (ic_lsize == 16)
r4k_blast_icache = blast_icache16;
else if (ic_lsize == 32) {
if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) &&
cpu_is_r4600_v1_x())
r4k_blast_icache = blast_r4600_v1_icache32;
else if (TX49XX_ICACHE_INDEX_INV_WAR)
r4k_blast_icache = tx49_blast_icache32;