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MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config option
Use a new config option to enable TX49XX I-cache index invalidate workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
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142439b052
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24a1c023f3
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@ -890,6 +890,7 @@ config MACH_TX39XX
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config MACH_TX49XX
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config MACH_TX49XX
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bool "Toshiba TX49 series based machines"
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bool "Toshiba TX49 series based machines"
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select WAR_TX49XX_ICACHE_INDEX_INV
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config MIKROTIK_RB532
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config MIKROTIK_RB532
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bool "Mikrotik RB532 boards"
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bool "Mikrotik RB532 boards"
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@ -2657,6 +2658,14 @@ config WAR_R4600_V1_HIT_CACHEOP
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config WAR_R4600_V2_HIT_CACHEOP
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config WAR_R4600_V2_HIT_CACHEOP
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bool
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bool
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# From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
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# the line which this instruction itself exists, the following
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# operation is not guaranteed."
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#
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# Workaround: do two phase flushing for Index_Invalidate_I
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config WAR_TX49XX_ICACHE_INDEX_INV
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bool
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#
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#
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# - Highmem only makes sense for the 32-bit kernel.
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# - Highmem only makes sense for the 32-bit kernel.
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# - The current highmem code will only work properly on physically indexed
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# - The current highmem code will only work properly on physically indexed
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@ -11,7 +11,6 @@
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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#define TX49XX_ICACHE_INDEX_INV_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define R10000_LLSC_WAR 0
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#define R10000_LLSC_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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@ -10,7 +10,6 @@
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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#define TX49XX_ICACHE_INDEX_INV_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define R10000_LLSC_WAR 0
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#define R10000_LLSC_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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@ -10,7 +10,6 @@
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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#define TX49XX_ICACHE_INDEX_INV_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define R10000_LLSC_WAR 0
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#define R10000_LLSC_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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@ -10,7 +10,6 @@
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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#define TX49XX_ICACHE_INDEX_INV_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define R10000_LLSC_WAR 1
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#define R10000_LLSC_WAR 1
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#define MIPS34K_MISSED_ITLB_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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@ -10,7 +10,6 @@
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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#define TX49XX_ICACHE_INDEX_INV_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define R10000_LLSC_WAR 1
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#define R10000_LLSC_WAR 1
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#define MIPS34K_MISSED_ITLB_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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@ -7,7 +7,6 @@
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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#define TX49XX_ICACHE_INDEX_INV_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#ifdef CONFIG_CPU_R10000
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#ifdef CONFIG_CPU_R10000
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#define R10000_LLSC_WAR 1
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#define R10000_LLSC_WAR 1
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@ -10,7 +10,6 @@
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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#define TX49XX_ICACHE_INDEX_INV_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 1
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#define ICACHE_REFILLS_WORKAROUND_WAR 1
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#define R10000_LLSC_WAR 0
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#define R10000_LLSC_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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@ -10,7 +10,6 @@
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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#define TX49XX_ICACHE_INDEX_INV_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 1
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#define ICACHE_REFILLS_WORKAROUND_WAR 1
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#define R10000_LLSC_WAR 0
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#define R10000_LLSC_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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@ -10,7 +10,6 @@
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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#define TX49XX_ICACHE_INDEX_INV_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define R10000_LLSC_WAR 0
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#define R10000_LLSC_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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@ -10,7 +10,6 @@
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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#define TX49XX_ICACHE_INDEX_INV_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define R10000_LLSC_WAR 0
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#define R10000_LLSC_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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@ -24,7 +24,6 @@ extern int sb1250_m3_workaround_needed(void);
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#endif
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#endif
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#define TX49XX_ICACHE_INDEX_INV_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define R10000_LLSC_WAR 0
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#define R10000_LLSC_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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@ -10,7 +10,6 @@
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#define BCM1250_M3_WAR 0
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define SIBYTE_1956_WAR 0
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#define TX49XX_ICACHE_INDEX_INV_WAR 1
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define R10000_LLSC_WAR 0
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#define R10000_LLSC_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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@ -93,17 +93,6 @@
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#error Check setting of SIBYTE_1956_WAR for your platform
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#error Check setting of SIBYTE_1956_WAR for your platform
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#endif
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#endif
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/*
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* From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
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* the line which this instruction itself exists, the following
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* operation is not guaranteed."
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*
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* Workaround: do two phase flushing for Index_Invalidate_I
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*/
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#ifndef TX49XX_ICACHE_INDEX_INV_WAR
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#error Check setting of TX49XX_ICACHE_INDEX_INV_WAR for your platform
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#endif
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/*
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/*
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* The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
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* The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
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* opposes it being called that) where invalid instructions in the same
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* opposes it being called that) where invalid instructions in the same
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@ -239,7 +239,7 @@ static void r4k_blast_dcache_setup(void)
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r4k_blast_dcache = blast_dcache128;
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r4k_blast_dcache = blast_dcache128;
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}
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}
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/* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
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/* force code alignment (used for CONFIG_WAR_TX49XX_ICACHE_INDEX_INV) */
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#define JUMP_TO_ALIGN(order) \
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#define JUMP_TO_ALIGN(order) \
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__asm__ __volatile__( \
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__asm__ __volatile__( \
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"b\t1f\n\t" \
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"b\t1f\n\t" \
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@ -371,7 +371,7 @@ static void r4k_blast_icache_page_indexed_setup(void)
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cpu_is_r4600_v1_x())
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cpu_is_r4600_v1_x())
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r4k_blast_icache_page_indexed =
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r4k_blast_icache_page_indexed =
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blast_icache32_r4600_v1_page_indexed;
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blast_icache32_r4600_v1_page_indexed;
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else if (TX49XX_ICACHE_INDEX_INV_WAR)
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else if (IS_ENABLED(CONFIG_WAR_TX49XX_ICACHE_INDEX_INV))
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r4k_blast_icache_page_indexed =
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r4k_blast_icache_page_indexed =
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tx49_blast_icache32_page_indexed;
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tx49_blast_icache32_page_indexed;
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else if (current_cpu_type() == CPU_LOONGSON2EF)
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else if (current_cpu_type() == CPU_LOONGSON2EF)
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@ -399,7 +399,7 @@ static void r4k_blast_icache_setup(void)
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if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) &&
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if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) &&
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cpu_is_r4600_v1_x())
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cpu_is_r4600_v1_x())
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r4k_blast_icache = blast_r4600_v1_icache32;
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r4k_blast_icache = blast_r4600_v1_icache32;
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else if (TX49XX_ICACHE_INDEX_INV_WAR)
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else if (IS_ENABLED(CONFIG_WAR_TX49XX_ICACHE_INDEX_INV))
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r4k_blast_icache = tx49_blast_icache32;
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r4k_blast_icache = tx49_blast_icache32;
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else if (current_cpu_type() == CPU_LOONGSON2EF)
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else if (current_cpu_type() == CPU_LOONGSON2EF)
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r4k_blast_icache = loongson2_blast_icache32;
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r4k_blast_icache = loongson2_blast_icache32;
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