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MIPS: Remove MIPS4K_ICACHE_REFILL_WAR and MIPS_CACHE_SYNC_WAR

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Neither MIPS4K_ICACHE_REFILL_WAR nor MIPS_CACHE_SYNC_WAR are implemented,
so removing defines for it won't change anything.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Thomas Bogendoerfer 2020-08-24 18:32:46 +02:00
parent 44def3426e
commit 142439b052
13 changed files with 0 additions and 59 deletions
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2
arch/mips/include/asm/mach-cavium-octeon/war.h
View file

@ -11,8 +11,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0

2
arch/mips/include/asm/mach-generic/war.h
View file

@ -10,8 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0

2
arch/mips/include/asm/mach-ip22/war.h
View file

@ -10,8 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0

2
arch/mips/include/asm/mach-ip27/war.h
View file

@ -10,8 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 1

2
arch/mips/include/asm/mach-ip28/war.h
View file

@ -10,8 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 1

2
arch/mips/include/asm/mach-ip30/war.h
View file

@ -7,8 +7,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#ifdef CONFIG_CPU_R10000

2
arch/mips/include/asm/mach-ip32/war.h
View file

@ -10,8 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 1
#define R10000_LLSC_WAR 0

2
arch/mips/include/asm/mach-malta/war.h
View file

@ -10,8 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 1
#define MIPS_CACHE_SYNC_WAR 1
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 1
#define R10000_LLSC_WAR 0

2
arch/mips/include/asm/mach-rc32434/war.h
View file

@ -10,8 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 1
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0

2
arch/mips/include/asm/mach-rm/war.h
View file

@ -10,8 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0

2
arch/mips/include/asm/mach-sibyte/war.h
View file

@ -24,8 +24,6 @@ extern int sb1250_m3_workaround_needed(void);
#endif
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0

2
arch/mips/include/asm/mach-tx49xx/war.h
View file

@ -10,8 +10,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 1
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0

35
arch/mips/include/asm/war.h
View file

@ -93,41 +93,6 @@
#error Check setting of SIBYTE_1956_WAR for your platform
#endif
/*
* Fill buffers not flushed on CACHE instructions
*
* Hit_Invalidate_I cacheops invalidate an icache line but the refill
* for that line can get stale data from the fill buffer instead of
* accessing memory if the previous icache miss was also to that line.
*
* Workaround: generate an icache refill from a different line
*
* Affects:
* MIPS 4K RTL revision <3.0, PRID revision <4
*/
#ifndef MIPS4K_ICACHE_REFILL_WAR
#error Check setting of MIPS4K_ICACHE_REFILL_WAR for your platform
#endif
/*
* Missing implicit forced flush of evictions caused by CACHE
* instruction
*
* Evictions caused by a CACHE instructions are not forced on to the
* bus. The BIU gives higher priority to fetches than to the data from
* the eviction buffer and no collision detection is performed between
* fetches and pending data from the eviction buffer.
*
* Workaround: Execute a SYNC instruction after the cache instruction
*
* Affects:
* MIPS 5Kc,5Kf RTL revision <2.3, PRID revision <8
* MIPS 20Kc RTL revision <4.0, PRID revision <?
*/
#ifndef MIPS_CACHE_SYNC_WAR
#error Check setting of MIPS_CACHE_SYNC_WAR for your platform
#endif
/*
* From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
* the line which this instruction itself exists, the following