freebsd-src/sys/riscv
Mitchell Horne d7adf3b47a riscv: fix L0 PTE setup (Sv48)
Per the Privilege Spec, the Accessed (A) or Dirty (D) bits must only be
set for a leaf PTE.

It seems newer versions of QEMU have started to enforce this
requirement, and without this change, pmap_bootstrap() hangs when
switching to Sv48 mode.

Reviewed by:	jrtc27, markj
MFC after:	3 days
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D45210
2024-05-15 14:07:33 -03:00
..
allwinner sys: Remove $FreeBSD$: one-line sh pattern 2023-08-16 11:54:58 -06:00
conf jh7110: enable MMC driver 2024-05-07 13:02:57 -03:00
include riscv: Convert local interrupt controller to a newbus PIC 2024-01-24 23:49:54 +00:00
riscv riscv: fix L0 PTE setup (Sv48) 2024-05-15 14:07:33 -03:00
sifive hwreset: Move reset code in dev/hwreset 2024-01-10 19:20:28 +01:00
starfive jh7110: Add StarFive JH7110 clock/reset generator drivers 2024-05-07 13:07:36 -03:00