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61e2161367
Each bus gets 1 MB of address space; the actual base address for an
MCFG bus range is the address from the table plus the starting bus
number times 1 MB.
The PCI spec is unclear on this point, but this change matches what
Linux does, which is likely enough of a de facto standard regardless
of what any de jure standard might attempt to say.
Fixes: f54a3890b1
("x86: Support multiple PCI MCFG regions")
Reviewed by: jhb
Differential Revision: https://reviews.freebsd.org/D43206
388 lines
10 KiB
C
388 lines
10 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
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* Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
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* Copyright (c) 2000, BSDi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/sysctl.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/pci_cfgreg.h>
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struct pcie_mcfg_region {
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char *base;
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uint16_t domain;
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uint8_t minbus;
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uint8_t maxbus;
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};
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static uint32_t pci_docfgregread(int domain, int bus, int slot, int func,
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int reg, int bytes);
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static struct pcie_mcfg_region *pcie_lookup_region(int domain, int bus);
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static int pciereg_cfgread(struct pcie_mcfg_region *region, int bus,
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unsigned slot, unsigned func, unsigned reg, unsigned bytes);
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static void pciereg_cfgwrite(struct pcie_mcfg_region *region, int bus,
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unsigned slot, unsigned func, unsigned reg, int data,
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unsigned bytes);
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static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
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static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
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SYSCTL_DECL(_hw_pci);
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/*
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* For amd64 we assume that type 1 I/O port-based access always works.
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* If an ACPI MCFG table exists, pcie_cfgregopen() will be called to
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* switch to memory-mapped access.
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*/
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int cfgmech = CFGMECH_1;
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static struct pcie_mcfg_region *mcfg_regions;
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static int mcfg_numregions;
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static uint32_t pcie_badslots;
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static struct mtx pcicfg_mtx;
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MTX_SYSINIT(pcicfg_mtx, &pcicfg_mtx, "pcicfg_mtx", MTX_SPIN);
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static int mcfg_enable = 1;
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SYSCTL_INT(_hw_pci, OID_AUTO, mcfg, CTLFLAG_RDTUN, &mcfg_enable, 0,
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"Enable support for PCI-e memory mapped config access");
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int
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pci_cfgregopen(void)
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{
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return (1);
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}
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static struct pcie_mcfg_region *
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pcie_lookup_region(int domain, int bus)
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{
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for (int i = 0; i < mcfg_numregions; i++)
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if (mcfg_regions[i].domain == domain &&
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bus >= mcfg_regions[i].minbus &&
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bus <= mcfg_regions[i].maxbus)
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return (&mcfg_regions[i]);
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return (NULL);
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}
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static uint32_t
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pci_docfgregread(int domain, int bus, int slot, int func, int reg, int bytes)
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{
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if (domain == 0 && bus == 0 && (1 << slot & pcie_badslots) != 0)
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return (pcireg_cfgread(bus, slot, func, reg, bytes));
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if (cfgmech == CFGMECH_PCIE) {
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struct pcie_mcfg_region *region;
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region = pcie_lookup_region(domain, bus);
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if (region != NULL)
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return (pciereg_cfgread(region, bus, slot, func, reg,
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bytes));
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}
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if (domain == 0)
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return (pcireg_cfgread(bus, slot, func, reg, bytes));
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else
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return (-1);
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}
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/*
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* Read configuration space register
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*/
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u_int32_t
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pci_cfgregread(int domain, int bus, int slot, int func, int reg, int bytes)
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{
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uint32_t line;
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/*
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* Some BIOS writers seem to want to ignore the spec and put
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* 0 in the intline rather than 255 to indicate none. Some use
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* numbers in the range 128-254 to indicate something strange and
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* apparently undocumented anywhere. Assume these are completely bogus
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* and map them to 255, which the rest of the PCI code recognizes as
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* as an invalid IRQ.
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*/
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if (reg == PCIR_INTLINE && bytes == 1) {
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line = pci_docfgregread(domain, bus, slot, func, PCIR_INTLINE,
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1);
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if (line == 0 || line >= 128)
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line = PCI_INVALID_IRQ;
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return (line);
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}
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return (pci_docfgregread(domain, bus, slot, func, reg, bytes));
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}
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/*
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* Write configuration space register
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*/
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void
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pci_cfgregwrite(int domain, int bus, int slot, int func, int reg, uint32_t data,
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int bytes)
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{
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if (domain == 0 && bus == 0 && (1 << slot & pcie_badslots) != 0) {
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pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
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return;
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}
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if (cfgmech == CFGMECH_PCIE) {
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struct pcie_mcfg_region *region;
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region = pcie_lookup_region(domain, bus);
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if (region != NULL) {
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pciereg_cfgwrite(region, bus, slot, func, reg, data,
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bytes);
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return;
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}
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}
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if (domain == 0)
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pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
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}
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/*
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* Configuration space access using direct register operations
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*/
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/* enable configuration space accesses and return data port address */
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static int
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pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
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{
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int dataport = 0;
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if (bus <= PCI_BUSMAX && slot <= PCI_SLOTMAX && func <= PCI_FUNCMAX &&
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(unsigned)reg <= PCI_REGMAX && bytes != 3 &&
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(unsigned)bytes <= 4 && (reg & (bytes - 1)) == 0) {
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outl(CONF1_ADDR_PORT, (1U << 31) | (bus << 16) | (slot << 11)
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| (func << 8) | (reg & ~0x03));
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dataport = CONF1_DATA_PORT + (reg & 0x03);
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}
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return (dataport);
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}
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/* disable configuration space accesses */
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static void
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pci_cfgdisable(void)
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{
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/*
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* Do nothing. Writing a 0 to the address port can apparently
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* confuse some bridges and cause spurious access failures.
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*/
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}
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static int
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pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
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{
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int data = -1;
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int port;
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mtx_lock_spin(&pcicfg_mtx);
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port = pci_cfgenable(bus, slot, func, reg, bytes);
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if (port != 0) {
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switch (bytes) {
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case 1:
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data = inb(port);
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break;
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case 2:
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data = inw(port);
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break;
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case 4:
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data = inl(port);
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break;
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}
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pci_cfgdisable();
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}
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mtx_unlock_spin(&pcicfg_mtx);
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return (data);
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}
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static void
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pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
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{
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int port;
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mtx_lock_spin(&pcicfg_mtx);
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port = pci_cfgenable(bus, slot, func, reg, bytes);
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if (port != 0) {
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switch (bytes) {
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case 1:
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outb(port, data);
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break;
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case 2:
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outw(port, data);
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break;
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case 4:
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outl(port, data);
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break;
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}
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pci_cfgdisable();
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}
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mtx_unlock_spin(&pcicfg_mtx);
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}
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static void
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pcie_init_badslots(struct pcie_mcfg_region *region)
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{
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uint32_t val1, val2;
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int slot;
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/*
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* On some AMD systems, some of the devices on bus 0 are
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* inaccessible using memory-mapped PCI config access. Walk
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* bus 0 looking for such devices. For these devices, we will
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* fall back to using type 1 config access instead.
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*/
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if (pci_cfgregopen() != 0) {
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for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
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val1 = pcireg_cfgread(0, slot, 0, 0, 4);
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if (val1 == 0xffffffff)
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continue;
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val2 = pciereg_cfgread(region, 0, slot, 0, 0, 4);
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if (val2 != val1)
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pcie_badslots |= (1 << slot);
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}
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}
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}
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int
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pcie_cfgregopen(uint64_t base, uint16_t domain, uint8_t minbus, uint8_t maxbus)
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{
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struct pcie_mcfg_region *region;
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if (!mcfg_enable)
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return (0);
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if (bootverbose)
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printf("PCI: MCFG domain %u bus %u-%u base @ 0x%lx\n",
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domain, minbus, maxbus, base);
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/* Resize the array. */
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mcfg_regions = realloc(mcfg_regions,
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sizeof(*mcfg_regions) * (mcfg_numregions + 1), M_DEVBUF, M_WAITOK);
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region = &mcfg_regions[mcfg_numregions];
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/* XXX: We should make sure this really fits into the direct map. */
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region->base = pmap_mapdev_pciecfg(base + (minbus << 20), (maxbus + 1 - minbus) << 20);
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region->domain = domain;
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region->minbus = minbus;
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region->maxbus = maxbus;
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mcfg_numregions++;
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cfgmech = CFGMECH_PCIE;
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if (domain == 0 && minbus == 0)
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pcie_init_badslots(region);
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return (1);
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}
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#define PCIE_VADDR(base, reg, bus, slot, func) \
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((base) + \
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((((bus) & 0xff) << 20) | \
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(((slot) & 0x1f) << 15) | \
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(((func) & 0x7) << 12) | \
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((reg) & 0xfff)))
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/*
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* AMD BIOS And Kernel Developer's Guides for CPU families starting with 10h
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* have a requirement that all accesses to the memory mapped PCI configuration
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* space are done using AX class of registers.
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* Since other vendors do not currently have any contradicting requirements
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* the AMD access pattern is applied universally.
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*/
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static int
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pciereg_cfgread(struct pcie_mcfg_region *region, int bus, unsigned slot,
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unsigned func, unsigned reg, unsigned bytes)
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{
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char *va;
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int data = -1;
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MPASS(bus >= region->minbus && bus <= region->maxbus);
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if (slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCIE_REGMAX)
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return (-1);
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va = PCIE_VADDR(region->base, reg, bus - region->minbus, slot, func);
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switch (bytes) {
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case 4:
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__asm("movl %1, %0" : "=a" (data)
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: "m" (*(volatile uint32_t *)va));
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break;
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case 2:
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__asm("movzwl %1, %0" : "=a" (data)
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: "m" (*(volatile uint16_t *)va));
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break;
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case 1:
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__asm("movzbl %1, %0" : "=a" (data)
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: "m" (*(volatile uint8_t *)va));
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break;
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}
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return (data);
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}
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static void
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pciereg_cfgwrite(struct pcie_mcfg_region *region, int bus, unsigned slot,
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unsigned func, unsigned reg, int data, unsigned bytes)
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{
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char *va;
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MPASS(bus >= region->minbus && bus <= region->maxbus);
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if (slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCIE_REGMAX)
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return;
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va = PCIE_VADDR(region->base, reg, bus - region->minbus, slot, func);
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switch (bytes) {
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case 4:
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__asm("movl %1, %0" : "=m" (*(volatile uint32_t *)va)
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: "a" (data));
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break;
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case 2:
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__asm("movw %1, %0" : "=m" (*(volatile uint16_t *)va)
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: "a" ((uint16_t)data));
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break;
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case 1:
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__asm("movb %1, %0" : "=m" (*(volatile uint8_t *)va)
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: "a" ((uint8_t)data));
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break;
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}
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}
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